Merge branches 'rmobile/ag5' and 'rmobile/mackerel' into rmobile-latest
This commit is contained in:
Paul Mundt
commit
598e227ea9
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@ -29,14 +29,20 @@
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#include <linux/gpio.h>
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#include <linux/input.h>
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#include <linux/io.h>
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#include <linux/i2c.h>
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#include <linux/leds.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/physmap.h>
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#include <linux/smsc911x.h>
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#include <linux/sh_intc.h>
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#include <linux/tca6416_keypad.h>
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#include <linux/usb/r8a66597.h>
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#include <video/sh_mobile_lcdc.h>
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#include <sound/sh_fsi.h>
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#include <mach/common.h>
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#include <mach/sh7372.h>
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@ -132,6 +138,21 @@
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* CN31 is used as Host in Linux.
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*/
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/*
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* FIXME !!
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*
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* gpio_no_direction
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* are quick_hack.
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*
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* current gpio frame work doesn't have
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* the method to control only pull up/down/free.
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* this function should be replaced by correct gpio function
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*/
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static void __init gpio_no_direction(u32 addr)
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{
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__raw_writeb(0x00, addr);
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}
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/* MTD */
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static struct mtd_partition nor_flash_partitions[] = {
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{
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@ -309,11 +330,138 @@ static struct platform_device usb1_host_device = {
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.resource = usb1_host_resources,
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};
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/* LED */
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static struct gpio_led mackerel_leds[] = {
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{
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.name = "led0",
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.gpio = GPIO_PORT0,
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.default_state = LEDS_GPIO_DEFSTATE_ON,
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},
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{
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.name = "led1",
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.gpio = GPIO_PORT1,
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.default_state = LEDS_GPIO_DEFSTATE_ON,
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},
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{
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.name = "led2",
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.gpio = GPIO_PORT2,
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.default_state = LEDS_GPIO_DEFSTATE_ON,
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},
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{
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.name = "led3",
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.gpio = GPIO_PORT159,
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.default_state = LEDS_GPIO_DEFSTATE_ON,
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}
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};
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static struct gpio_led_platform_data mackerel_leds_pdata = {
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.leds = mackerel_leds,
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.num_leds = ARRAY_SIZE(mackerel_leds),
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};
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static struct platform_device leds_device = {
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.name = "leds-gpio",
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.id = 0,
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.dev = {
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.platform_data = &mackerel_leds_pdata,
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},
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};
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/* FSI */
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#define IRQ_FSI evt2irq(0x1840)
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static struct sh_fsi_platform_info fsi_info = {
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.porta_flags = SH_FSI_BRS_INV |
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SH_FSI_OUT_SLAVE_MODE |
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SH_FSI_IN_SLAVE_MODE |
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SH_FSI_OFMT(PCM) |
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SH_FSI_IFMT(PCM),
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};
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static struct resource fsi_resources[] = {
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[0] = {
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.name = "FSI",
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.start = 0xFE3C0000,
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.end = 0xFE3C0400 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_FSI,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device fsi_device = {
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.name = "sh_fsi2",
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.id = -1,
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.num_resources = ARRAY_SIZE(fsi_resources),
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.resource = fsi_resources,
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.dev = {
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.platform_data = &fsi_info,
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},
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};
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static struct platform_device fsi_ak4643_device = {
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.name = "sh_fsi2_a_ak4643",
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};
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static struct platform_device *mackerel_devices[] __initdata = {
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&nor_flash_device,
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&smc911x_device,
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&lcdc_device,
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&usb1_host_device,
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&leds_device,
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&fsi_device,
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&fsi_ak4643_device,
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};
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/* Keypad Initialization */
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#define KEYPAD_BUTTON(ev_type, ev_code, act_low) \
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{ \
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.type = ev_type, \
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.code = ev_code, \
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.active_low = act_low, \
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}
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#define KEYPAD_BUTTON_LOW(event_code) KEYPAD_BUTTON(EV_KEY, event_code, 1)
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static struct tca6416_button mackerel_gpio_keys[] = {
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KEYPAD_BUTTON_LOW(KEY_HOME),
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KEYPAD_BUTTON_LOW(KEY_MENU),
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KEYPAD_BUTTON_LOW(KEY_BACK),
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KEYPAD_BUTTON_LOW(KEY_POWER),
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};
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static struct tca6416_keys_platform_data mackerel_tca6416_keys_info = {
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.buttons = mackerel_gpio_keys,
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.nbuttons = ARRAY_SIZE(mackerel_gpio_keys),
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.rep = 1,
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.use_polling = 0,
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.pinmask = 0x000F,
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};
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/* I2C */
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#define IRQ9 evt2irq(0x0320)
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static struct i2c_board_info i2c0_devices[] = {
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{
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I2C_BOARD_INFO("ak4643", 0x13),
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},
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/* Keypad */
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{
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I2C_BOARD_INFO("tca6408-keys", 0x20),
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.platform_data = &mackerel_tca6416_keys_info,
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.irq = IRQ9,
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},
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};
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#define IRQ21 evt2irq(0x32a0)
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static struct i2c_board_info i2c1_devices[] = {
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/* Accelerometer */
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{
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I2C_BOARD_INFO("adxl34x", 0x53),
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.irq = IRQ21,
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},
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};
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static struct map_desc mackerel_io_desc[] __initdata = {
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@ -337,6 +485,8 @@ static void __init mackerel_map_io(void)
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shmobile_setup_console();
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}
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#define GPIO_PORT9CR 0xE6051009
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#define GPIO_PORT10CR 0xE605100A
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static void __init mackerel_init(void)
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{
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sh7372_pinmux_init();
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@ -394,6 +544,33 @@ static void __init mackerel_init(void)
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/* setup USB phy */
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__raw_writew(0x8a0a, 0xE6058130); /* USBCR2 */
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/* enable FSI2 port A (ak4643) */
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gpio_request(GPIO_FN_FSIAIBT, NULL);
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gpio_request(GPIO_FN_FSIAILR, NULL);
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gpio_request(GPIO_FN_FSIAISLD, NULL);
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gpio_request(GPIO_FN_FSIAOSLD, NULL);
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gpio_request(GPIO_PORT161, NULL);
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gpio_direction_output(GPIO_PORT161, 0); /* slave */
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gpio_request(GPIO_PORT9, NULL);
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gpio_request(GPIO_PORT10, NULL);
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gpio_no_direction(GPIO_PORT9CR); /* FSIAOBT needs no direction */
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gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
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intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
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/* enable Keypad */
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gpio_request(GPIO_FN_IRQ9_42, NULL);
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set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
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/* enable Accelerometer */
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gpio_request(GPIO_FN_IRQ21, NULL);
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set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
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i2c_register_board_info(0, i2c0_devices,
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ARRAY_SIZE(i2c0_devices));
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i2c_register_board_info(1, i2c1_devices,
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ARRAY_SIZE(i2c1_devices));
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sh7372_add_standard_devices();
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@ -23,37 +23,241 @@
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#include <mach/common.h>
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#include <asm/clkdev.h>
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#define FRQCRA 0xe6150000
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#define FRQCRB 0xe6150004
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#define FRQCRD 0xe61500e4
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#define VCLKCR1 0xe6150008
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#define VCLKCR2 0xe615000C
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#define VCLKCR3 0xe615001C
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#define ZBCKCR 0xe6150010
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#define FLCKCR 0xe6150014
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#define SD0CKCR 0xe6150074
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#define SD1CKCR 0xe6150078
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#define SD2CKCR 0xe615007C
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#define FSIACKCR 0xe6150018
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#define FSIBCKCR 0xe6150090
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#define SUBCKCR 0xe6150080
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#define SPUACKCR 0xe6150084
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#define SPUVCKCR 0xe6150094
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#define MSUCKCR 0xe6150088
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#define HSICKCR 0xe615008C
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#define MFCK1CR 0xe6150098
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#define MFCK2CR 0xe615009C
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#define DSITCKCR 0xe6150060
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#define DSI0PCKCR 0xe6150064
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#define DSI1PCKCR 0xe6150068
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#define DSI0PHYCR 0xe615006C
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#define DSI1PHYCR 0xe6150070
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#define PLLECR 0xe61500d0
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#define PLL0CR 0xe61500d8
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#define PLL1CR 0xe6150028
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#define PLL2CR 0xe615002c
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#define PLL3CR 0xe61500dc
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#define SMSTPCR0 0xe6150130
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#define SMSTPCR1 0xe6150134
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#define SMSTPCR2 0xe6150138
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR4 0xe6150140
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#define SMSTPCR5 0xe6150144
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#define CKSCR 0xe61500c0
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/* Fixed 32 KHz root clock from EXTALR pin */
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static struct clk r_clk = {
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.rate = 32768,
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};
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/* Temporarily fixed 48 MHz SUB clock */
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static struct clk sub_clk = {
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.rate = 48000000,
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/*
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* 26MHz default rate for the EXTAL1 root input clock.
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* If needed, reset this with clk_set_rate() from the platform code.
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*/
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struct clk sh73a0_extal1_clk = {
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.rate = 26000000,
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};
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/* Temporarily fixed 104 MHz HP clock */
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static struct clk hp_clk = {
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.rate = 104000000,
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/*
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* 48MHz default rate for the EXTAL2 root input clock.
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* If needed, reset this with clk_set_rate() from the platform code.
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*/
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struct clk sh73a0_extal2_clk = {
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.rate = 48000000,
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};
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/* A fixed divide-by-2 block */
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static unsigned long div2_recalc(struct clk *clk)
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{
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return clk->parent->rate / 2;
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}
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static struct clk_ops div2_clk_ops = {
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.recalc = div2_recalc,
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};
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/* Divide extal1 by two */
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static struct clk extal1_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &sh73a0_extal1_clk,
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};
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/* Divide extal2 by two */
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static struct clk extal2_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &sh73a0_extal2_clk,
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};
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static struct clk_ops main_clk_ops = {
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.recalc = followparent_recalc,
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};
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/* Main clock */
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static struct clk main_clk = {
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.ops = &main_clk_ops,
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};
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/* PLL0, PLL1, PLL2, PLL3 */
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static unsigned long pll_recalc(struct clk *clk)
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{
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unsigned long mult = 1;
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|
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if (__raw_readl(PLLECR) & (1 << clk->enable_bit))
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mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
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return clk->parent->rate * mult;
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}
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static struct clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
|
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|
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static struct clk pll0_clk = {
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.ops = &pll_clk_ops,
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||||
.flags = CLK_ENABLE_ON_INIT,
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.parent = &main_clk,
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.enable_reg = (void __iomem *)PLL0CR,
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.enable_bit = 0,
|
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};
|
||||
|
||||
static struct clk pll1_clk = {
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.ops = &pll_clk_ops,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
.parent = &main_clk,
|
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.enable_reg = (void __iomem *)PLL1CR,
|
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.enable_bit = 1,
|
||||
};
|
||||
|
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static struct clk pll2_clk = {
|
||||
.ops = &pll_clk_ops,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
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.parent = &main_clk,
|
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.enable_reg = (void __iomem *)PLL2CR,
|
||||
.enable_bit = 2,
|
||||
};
|
||||
|
||||
static struct clk pll3_clk = {
|
||||
.ops = &pll_clk_ops,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
.parent = &main_clk,
|
||||
.enable_reg = (void __iomem *)PLL3CR,
|
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.enable_bit = 3,
|
||||
};
|
||||
|
||||
/* Divide PLL1 by two */
|
||||
static struct clk pll1_div2_clk = {
|
||||
.ops = &div2_clk_ops,
|
||||
.parent = &pll1_clk,
|
||||
};
|
||||
|
||||
static struct clk *main_clks[] = {
|
||||
&r_clk,
|
||||
&sub_clk,
|
||||
&hp_clk,
|
||||
&sh73a0_extal1_clk,
|
||||
&sh73a0_extal2_clk,
|
||||
&extal1_div2_clk,
|
||||
&extal2_div2_clk,
|
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&main_clk,
|
||||
&pll0_clk,
|
||||
&pll1_clk,
|
||||
&pll2_clk,
|
||||
&pll3_clk,
|
||||
&pll1_div2_clk,
|
||||
};
|
||||
|
||||
enum { MSTP001,
|
||||
static void div4_kick(struct clk *clk)
|
||||
{
|
||||
unsigned long value;
|
||||
|
||||
/* set KICK bit in FRQCRB to update hardware setting */
|
||||
value = __raw_readl(FRQCRB);
|
||||
value |= (1 << 31);
|
||||
__raw_writel(value, FRQCRB);
|
||||
}
|
||||
|
||||
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
|
||||
24, 0, 36, 48 };
|
||||
|
||||
static struct clk_div_mult_table div4_div_mult_table = {
|
||||
.divisors = divisors,
|
||||
.nr_divisors = ARRAY_SIZE(divisors),
|
||||
};
|
||||
|
||||
static struct clk_div4_table div4_table = {
|
||||
.div_mult_table = &div4_div_mult_table,
|
||||
.kick = div4_kick,
|
||||
};
|
||||
|
||||
enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
|
||||
DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR };
|
||||
|
||||
#define DIV4(_reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
|
||||
|
||||
static struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_M3] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
|
||||
[DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
|
||||
[DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0),
|
||||
[DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0),
|
||||
[DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0),
|
||||
[DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0),
|
||||
[DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0),
|
||||
};
|
||||
|
||||
enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
|
||||
DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
|
||||
DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
|
||||
DIV6_SPUA, DIV6_SPUV, DIV6_MSU,
|
||||
DIV6_HSI, DIV6_MFG1, DIV6_MFG2,
|
||||
DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
|
||||
DIV6_NR };
|
||||
|
||||
static struct clk div6_clks[DIV6_NR] = {
|
||||
[DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0),
|
||||
[DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0),
|
||||
[DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0),
|
||||
[DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, 0),
|
||||
[DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0),
|
||||
[DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0),
|
||||
[DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
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[DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
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[DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0),
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[DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0),
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[DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0),
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[DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0),
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[DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0),
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||||
[DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0),
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||||
[DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0),
|
||||
[DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0),
|
||||
[DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0),
|
||||
[DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0),
|
||||
[DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0),
|
||||
[DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0),
|
||||
};
|
||||
|
||||
enum { MSTP001,
|
||||
MSTP116,
|
||||
MSTP219, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
MSTP219,
|
||||
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
MSTP331, MSTP329, MSTP323,
|
||||
MSTP411, MSTP410, MSTP403,
|
||||
MSTP_NR };
|
||||
|
|
@ -62,27 +266,30 @@ enum { MSTP001,
|
|||
SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP001] = MSTP(&hp_clk, SMSTPCR0, 1, 0), /* I2C2 */
|
||||
[MSTP116] = MSTP(&hp_clk, SMSTPCR1, 16, 0), /* I2C0 */
|
||||
[MSTP219] = MSTP(&sub_clk, SMSTPCR2, 19, 0), /* SCIFA7 */
|
||||
[MSTP207] = MSTP(&sub_clk, SMSTPCR2, 7, 0), /* SCIFA5 */
|
||||
[MSTP206] = MSTP(&sub_clk, SMSTPCR2, 6, 0), /* SCIFB */
|
||||
[MSTP204] = MSTP(&sub_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
|
||||
[MSTP203] = MSTP(&sub_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
|
||||
[MSTP202] = MSTP(&sub_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
|
||||
[MSTP201] = MSTP(&sub_clk, SMSTPCR2, 1, 0), /* SCIFA3 */
|
||||
[MSTP200] = MSTP(&sub_clk, SMSTPCR2, 0, 0), /* SCIFA4 */
|
||||
[MSTP331] = MSTP(&sub_clk, SMSTPCR3, 31, 0), /* SCIFA6 */
|
||||
[MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
|
||||
[MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
|
||||
[MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
|
||||
[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
|
||||
[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
|
||||
[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
|
||||
[MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
|
||||
[MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
|
||||
[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
|
||||
[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
|
||||
[MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
|
||||
[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
|
||||
[MSTP323] = MSTP(&hp_clk, SMSTPCR3, 23, 0), /* I2C1 */
|
||||
[MSTP411] = MSTP(&hp_clk, SMSTPCR4, 11, 0), /* I2C3 */
|
||||
[MSTP410] = MSTP(&hp_clk, SMSTPCR4, 10, 0), /* I2C4 */
|
||||
[MSTP403] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* KEYSC0 */
|
||||
[MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
|
||||
[MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
|
||||
[MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
|
||||
};
|
||||
|
||||
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
|
||||
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("r_clk", &r_clk),
|
||||
|
||||
/* MSTP32 clocks */
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
|
||||
|
|
@ -106,9 +313,31 @@ void __init sh73a0_clock_init(void)
|
|||
{
|
||||
int k, ret = 0;
|
||||
|
||||
/* detect main clock parent */
|
||||
switch ((__raw_readl(CKSCR) >> 24) & 0x03) {
|
||||
case 0:
|
||||
main_clk.parent = &sh73a0_extal1_clk;
|
||||
break;
|
||||
case 1:
|
||||
main_clk.parent = &extal1_div2_clk;
|
||||
break;
|
||||
case 2:
|
||||
main_clk.parent = &sh73a0_extal2_clk;
|
||||
break;
|
||||
case 3:
|
||||
main_clk.parent = &extal2_div2_clk;
|
||||
break;
|
||||
}
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
|
||||
|
||||
|
|
|
|||
|
|
@ -34,5 +34,7 @@ extern void sh73a0_add_early_devices(void);
|
|||
extern void sh73a0_add_standard_devices(void);
|
||||
extern void sh73a0_clock_init(void);
|
||||
extern void sh73a0_pinmux_init(void);
|
||||
extern struct clk sh73a0_extal1_clk;
|
||||
extern struct clk sh73a0_extal2_clk;
|
||||
|
||||
#endif /* __ARCH_MACH_COMMON_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue