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MIPS: bitops: Use MIPS_ISA_REV, not #ifdefs 

Rather than #ifdef on CONFIG_CPU_* to determine whether the ins
instruction is supported we can simply check MIPS_ISA_REV to discover
whether we're targeting MIPSr2 or higher. Do so in order to clean up the
code.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org
This commit is contained in:
Paul Burton 2019-10-01 21:53:27 +00:00
parent 3d2920cf4f
commit 59361e9975
No known key found for this signature in database
GPG Key ID: 3EA79FACB57500DD
1 changed files with 4 additions and 9 deletions
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13
arch/mips/include/asm/bitops.h
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@ -19,6 +19,7 @@
#include <asm/byteorder.h> /* sigh ... */
#include <asm/compiler.h>
#include <asm/cpu-features.h>
#include <asm/isa-rev.h>
#include <asm/llsc.h>
#include <asm/sgidefs.h>
#include <asm/war.h>
@ -76,8 +77,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
return;
}
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
if (__builtin_constant_p(bit) && (bit >= 16)) {
if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(bit) && (bit >= 16)) {
loongson_llsc_mb();
do {
__asm__ __volatile__(
@ -90,7 +90,6 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
} while (unlikely(!temp));
return;
}
#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
loongson_llsc_mb();
do {
@ -143,8 +142,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
return;
}
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
if (__builtin_constant_p(bit)) {
if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(bit)) {
loongson_llsc_mb();
do {
__asm__ __volatile__(
@ -157,7 +155,6 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
} while (unlikely(!temp));
return;
}
#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
loongson_llsc_mb();
do {
@ -377,8 +374,7 @@ static inline int test_and_clear_bit(unsigned long nr,
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
: __LLSC_CLOBBER);
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
} else if (__builtin_constant_p(nr)) {
} else if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(nr)) {
loongson_llsc_mb();
do {
__asm__ __volatile__(
@ -390,7 +386,6 @@ static inline int test_and_clear_bit(unsigned long nr,
: "ir" (bit)
: __LLSC_CLOBBER);
} while (unlikely(!temp));
#endif
} else {
loongson_llsc_mb();
do {