net/mlx4: Fix typo, move similar defs to same location
Small code cleanup: 1. change MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN to MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN 2. put MLX4_SET_PORT_PRIO2TC and MLX4_SET_PORT_SCHEDULER in the same union with the other MLX4_SET_PORT_yyy Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: Amir Vadai <amirv@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1733,7 +1733,7 @@ void mlx4_en_stop_port(struct net_device *dev, int detach)
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/* Unregister Mac address for the port */
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/* Unregister Mac address for the port */
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mlx4_en_put_qp(priv);
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mlx4_en_put_qp(priv);
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if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN))
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if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
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mdev->mac_removed[priv->port] = 1;
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mdev->mac_removed[priv->port] = 1;
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/* Free RX Rings */
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/* Free RX Rings */
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@ -652,7 +652,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
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QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
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if (field & 1<<6)
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if (field & 1<<6)
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dev_cap->flags2 |= MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN;
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dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
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MLX4_GET(dev_cap->max_icm_sz, outbox,
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MLX4_GET(dev_cap->max_icm_sz, outbox,
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QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
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QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
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if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
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if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
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@ -154,10 +154,6 @@ enum {
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MLX4_CMD_QUERY_IF_STAT = 0X54,
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MLX4_CMD_QUERY_IF_STAT = 0X54,
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MLX4_CMD_SET_IF_STAT = 0X55,
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MLX4_CMD_SET_IF_STAT = 0X55,
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/* set port opcode modifiers */
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MLX4_SET_PORT_PRIO2TC = 0x8,
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MLX4_SET_PORT_SCHEDULER = 0x9,
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/* register/delete flow steering network rules */
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/* register/delete flow steering network rules */
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MLX4_QP_FLOW_STEERING_ATTACH = 0x65,
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MLX4_QP_FLOW_STEERING_ATTACH = 0x65,
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MLX4_QP_FLOW_STEERING_DETACH = 0x66,
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MLX4_QP_FLOW_STEERING_DETACH = 0x66,
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@ -182,6 +178,8 @@ enum {
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MLX4_SET_PORT_VLAN_TABLE = 0x3,
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MLX4_SET_PORT_VLAN_TABLE = 0x3,
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MLX4_SET_PORT_PRIO_MAP = 0x4,
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MLX4_SET_PORT_PRIO_MAP = 0x4,
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MLX4_SET_PORT_GID_TABLE = 0x5,
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MLX4_SET_PORT_GID_TABLE = 0x5,
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MLX4_SET_PORT_PRIO2TC = 0x8,
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MLX4_SET_PORT_SCHEDULER = 0x9,
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};
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};
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enum {
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enum {
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@ -155,7 +155,7 @@ enum {
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MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
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MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
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MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
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MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
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MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
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MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
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MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN = 1LL << 4,
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MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
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MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
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MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
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MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
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MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
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MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
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MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
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