hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment 

PLL0 runs at 4.8 GHz, i.e. EXTAL x 100.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2018-09-18 10:55:29 +02:00
parent 7c0043c0a4
commit 5915838b7a
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/clk/renesas/r8a77990-cpg-mssr.c
View File

@ -250,8 +250,8 @@ static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
/*
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
*--------------------------------------------------------------------
* 0 48 x 1 x100/4 x100/3 x100/3
* 1 48 x 1 x100/4 x100/3 x58/3
* 0 48 x 1 x100/1 x100/3 x100/3
* 1 48 x 1 x100/1 x100/3 x58/3
*/
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)