ARM: OMAP3: clock data: fill in some missing clockdomains
Several clocks are missing clockdomains. This can cause problems with the hwmod and power management code. Fill these in. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Matt Porter <mporter@ti.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com>
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@ -1394,6 +1394,7 @@ static struct clk cpefuse_fck = {
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.name = "cpefuse_fck",
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.ops = &clkops_omap2_dflt,
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.parent = &sys_ck,
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.clkdm_name = "core_l4_clkdm",
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
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.enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
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.recalc = &followparent_recalc,
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@ -1403,6 +1404,7 @@ static struct clk ts_fck = {
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.name = "ts_fck",
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.ops = &clkops_omap2_dflt,
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.parent = &omap_32k_fck,
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.clkdm_name = "core_l4_clkdm",
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
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.enable_bit = OMAP3430ES2_EN_TS_SHIFT,
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.recalc = &followparent_recalc,
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@ -1412,6 +1414,7 @@ static struct clk usbtll_fck = {
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.name = "usbtll_fck",
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.ops = &clkops_omap2_dflt_wait,
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.parent = &dpll5_m2_ck,
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.clkdm_name = "core_l4_clkdm",
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
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.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
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.recalc = &followparent_recalc,
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@ -1617,6 +1620,7 @@ static struct clk fshostusb_fck = {
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.name = "fshostusb_fck",
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.ops = &clkops_omap2_dflt_wait,
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.parent = &core_48m_fck,
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.clkdm_name = "core_l4_clkdm",
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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.enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
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.recalc = &followparent_recalc,
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@ -2043,6 +2047,7 @@ static struct clk omapctrl_ick = {
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
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.enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
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.flags = ENABLE_ON_INIT,
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.clkdm_name = "core_l4_clkdm",
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.recalc = &followparent_recalc,
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};
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@ -2094,6 +2099,7 @@ static struct clk usb_l4_ick = {
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.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
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.clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
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.clksel = usb_l4_clksel,
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.clkdm_name = "core_l4_clkdm",
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.recalc = &omap2_clksel_recalc,
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};
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