cmd64x: procfs code fixes/cleanups (take 2)
Fix several issues with the driver's procfs output: - when testing if channel is enabled, the code looks at the "simplex" bits, not at the real enable bits -- add #define for the primary channel enable bit; - UltraDMA modes 0, 1, 3 for slave drive reported incorrectly due to using the master drive's clock cycle resolution bit. While at it, also perform the following cleanups: - don't print extra newline before the first controller's dump; - correct the chipset names (from CMDxxx to PCI-xxx) - don't read from the registers which aren't used for dump; - better align the table column sizes; - rework UltraDMA mode dump code; - remove PIO mode dump code that has never been finished; - remove the duplicate interrupt status (the MRDMODE register bits mirror those those in the CFR and ARTTIM23 registers) and fold the dump into single line; - correct the style of the ?: operators... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Sergei Shtylyov
Bartlomiej Zolnierkiewicz
parent
7accbffdb8
commit
5826b318aa
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@ -1,5 +1,5 @@
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/*
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* linux/drivers/ide/pci/cmd64x.c Version 1.45 Mar 14, 2007
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* linux/drivers/ide/pci/cmd64x.c Version 1.46 Mar 16, 2007
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*
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* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
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* Due to massive hardware bugs, UltraDMA is only supported
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@ -38,9 +38,10 @@
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#define CFR 0x50
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#define CFR_INTR_CH0 0x04
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#define CNTRL 0x51
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#define CNTRL_DIS_RA0 0x40
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#define CNTRL_DIS_RA1 0x80
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#define CNTRL_ENA_2ND 0x08
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#define CNTRL_ENA_1ST 0x04
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#define CNTRL_ENA_2ND 0x08
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#define CNTRL_DIS_RA0 0x40
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#define CNTRL_DIS_RA1 0x80
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#define CMDTIM 0x52
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#define ARTTIM0 0x53
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@ -87,86 +88,67 @@ static int n_cmd_devs;
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static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
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{
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char *p = buf;
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u8 reg53 = 0, reg54 = 0, reg55 = 0, reg56 = 0; /* primary */
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u8 reg57 = 0, reg58 = 0, reg5b; /* secondary */
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u8 reg72 = 0, reg73 = 0; /* primary */
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u8 reg7a = 0, reg7b = 0; /* secondary */
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u8 reg50 = 0, reg71 = 0; /* extra */
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u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */
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u8 rev = 0;
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p += sprintf(p, "\nController: %d\n", index);
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p += sprintf(p, "CMD%x Chipset.\n", dev->device);
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p += sprintf(p, "PCI-%x Chipset.\n", dev->device);
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(void) pci_read_config_byte(dev, CFR, ®50);
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(void) pci_read_config_byte(dev, ARTTIM0, ®53);
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(void) pci_read_config_byte(dev, DRWTIM0, ®54);
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(void) pci_read_config_byte(dev, ARTTIM1, ®55);
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(void) pci_read_config_byte(dev, DRWTIM1, ®56);
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(void) pci_read_config_byte(dev, ARTTIM2, ®57);
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(void) pci_read_config_byte(dev, DRWTIM2, ®58);
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(void) pci_read_config_byte(dev, DRWTIM3, ®5b);
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(void) pci_read_config_byte(dev, CNTRL, ®51);
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(void) pci_read_config_byte(dev, ARTTIM23, ®57);
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(void) pci_read_config_byte(dev, MRDMODE, ®71);
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(void) pci_read_config_byte(dev, BMIDESR0, ®72);
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(void) pci_read_config_byte(dev, UDIDETCR0, ®73);
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(void) pci_read_config_byte(dev, BMIDESR1, ®7a);
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(void) pci_read_config_byte(dev, UDIDETCR1, ®7b);
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p += sprintf(p, "--------------- Primary Channel "
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"---------------- Secondary Channel "
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"-------------\n");
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p += sprintf(p, " %sabled "
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" %sabled\n",
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(reg72&0x80)?"dis":" en",
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(reg7a&0x80)?"dis":" en");
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p += sprintf(p, "--------------- drive0 "
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"--------- drive1 -------- drive0 "
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"---------- drive1 ------\n");
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p += sprintf(p, "DMA enabled: %s %s"
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" %s %s\n",
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(reg72&0x20)?"yes":"no ", (reg72&0x40)?"yes":"no ",
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(reg7a&0x20)?"yes":"no ", (reg7a&0x40)?"yes":"no ");
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/* PCI0643/6 originally didn't have the primary channel enable bit */
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(void) pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
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if ((dev->device == PCI_DEVICE_ID_CMD_643) ||
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(dev->device == PCI_DEVICE_ID_CMD_646 && rev < 3))
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reg51 |= CNTRL_ENA_1ST;
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p += sprintf(p, "DMA Mode: %s(%s) %s(%s)",
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(reg72&0x20)?((reg73&0x01)?"UDMA":" DMA"):" PIO",
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(reg72&0x20)?(
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((reg73&0x30)==0x30)?(((reg73&0x35)==0x35)?"3":"0"):
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((reg73&0x20)==0x20)?(((reg73&0x25)==0x25)?"3":"1"):
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((reg73&0x10)==0x10)?(((reg73&0x15)==0x15)?"4":"2"):
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((reg73&0x00)==0x00)?(((reg73&0x05)==0x05)?"5":"2"):
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"X"):"?",
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(reg72&0x40)?((reg73&0x02)?"UDMA":" DMA"):" PIO",
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(reg72&0x40)?(
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((reg73&0xC0)==0xC0)?(((reg73&0xC5)==0xC5)?"3":"0"):
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((reg73&0x80)==0x80)?(((reg73&0x85)==0x85)?"3":"1"):
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((reg73&0x40)==0x40)?(((reg73&0x4A)==0x4A)?"4":"2"):
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((reg73&0x00)==0x00)?(((reg73&0x0A)==0x0A)?"5":"2"):
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"X"):"?");
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p += sprintf(p, " %s(%s) %s(%s)\n",
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(reg7a&0x20)?((reg7b&0x01)?"UDMA":" DMA"):" PIO",
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(reg7a&0x20)?(
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((reg7b&0x30)==0x30)?(((reg7b&0x35)==0x35)?"3":"0"):
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((reg7b&0x20)==0x20)?(((reg7b&0x25)==0x25)?"3":"1"):
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((reg7b&0x10)==0x10)?(((reg7b&0x15)==0x15)?"4":"2"):
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((reg7b&0x00)==0x00)?(((reg7b&0x05)==0x05)?"5":"2"):
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"X"):"?",
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(reg7a&0x40)?((reg7b&0x02)?"UDMA":" DMA"):" PIO",
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(reg7a&0x40)?(
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((reg7b&0xC0)==0xC0)?(((reg7b&0xC5)==0xC5)?"3":"0"):
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((reg7b&0x80)==0x80)?(((reg7b&0x85)==0x85)?"3":"1"):
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((reg7b&0x40)==0x40)?(((reg7b&0x4A)==0x4A)?"4":"2"):
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((reg7b&0x00)==0x00)?(((reg7b&0x0A)==0x0A)?"5":"2"):
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"X"):"?" );
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p += sprintf(p, "PIO Mode: %s %s"
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" %s %s\n",
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"?", "?", "?", "?");
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p += sprintf(p, " %s %s\n",
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(reg50 & CFR_INTR_CH0) ? "interrupting" : "polling ",
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(reg57 & ARTTIM23_INTR_CH1) ? "interrupting" : "polling");
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p += sprintf(p, " %s %s\n",
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(reg71 & MRDMODE_INTR_CH0) ? "pending" : "clear ",
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(reg71 & MRDMODE_INTR_CH1) ? "pending" : "clear");
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p += sprintf(p, " %s %s\n",
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(reg71 & MRDMODE_BLK_CH0) ? "blocked" : "enabled",
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(reg71 & MRDMODE_BLK_CH1) ? "blocked" : "enabled");
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p += sprintf(p, "---------------- Primary Channel "
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"---------------- Secondary Channel ------------\n");
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p += sprintf(p, " %s %s\n",
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(reg51 & CNTRL_ENA_1ST) ? "enabled " : "disabled",
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(reg51 & CNTRL_ENA_2ND) ? "enabled " : "disabled");
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p += sprintf(p, "---------------- drive0 --------- drive1 "
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"-------- drive0 --------- drive1 ------\n");
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p += sprintf(p, "DMA enabled: %s %s"
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" %s %s\n",
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(reg72 & 0x20) ? "yes" : "no ", (reg72 & 0x40) ? "yes" : "no ",
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(reg7a & 0x20) ? "yes" : "no ", (reg7a & 0x40) ? "yes" : "no ");
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p += sprintf(p, "UltraDMA mode: %s (%c) %s (%c)",
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( reg73 & 0x01) ? " on" : "off",
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((reg73 & 0x30) == 0x30) ? ((reg73 & 0x04) ? '3' : '0') :
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((reg73 & 0x30) == 0x20) ? ((reg73 & 0x04) ? '3' : '1') :
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((reg73 & 0x30) == 0x10) ? ((reg73 & 0x04) ? '4' : '2') :
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((reg73 & 0x30) == 0x00) ? ((reg73 & 0x04) ? '5' : '2') : '?',
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( reg73 & 0x02) ? " on" : "off",
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((reg73 & 0xC0) == 0xC0) ? ((reg73 & 0x08) ? '3' : '0') :
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((reg73 & 0xC0) == 0x80) ? ((reg73 & 0x08) ? '3' : '1') :
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((reg73 & 0xC0) == 0x40) ? ((reg73 & 0x08) ? '4' : '2') :
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((reg73 & 0xC0) == 0x00) ? ((reg73 & 0x08) ? '5' : '2') : '?');
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p += sprintf(p, " %s (%c) %s (%c)\n",
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( reg7b & 0x01) ? " on" : "off",
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((reg7b & 0x30) == 0x30) ? ((reg7b & 0x04) ? '3' : '0') :
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((reg7b & 0x30) == 0x20) ? ((reg7b & 0x04) ? '3' : '1') :
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((reg7b & 0x30) == 0x10) ? ((reg7b & 0x04) ? '4' : '2') :
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((reg7b & 0x30) == 0x00) ? ((reg7b & 0x04) ? '5' : '2') : '?',
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( reg7b & 0x02) ? " on" : "off",
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((reg7b & 0xC0) == 0xC0) ? ((reg7b & 0x08) ? '3' : '0') :
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((reg7b & 0xC0) == 0x80) ? ((reg7b & 0x08) ? '3' : '1') :
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((reg7b & 0xC0) == 0x40) ? ((reg7b & 0x08) ? '4' : '2') :
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((reg7b & 0xC0) == 0x00) ? ((reg7b & 0x08) ? '5' : '2') : '?');
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p += sprintf(p, "Interrupt: %s, %s %s, %s\n",
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(reg71 & MRDMODE_BLK_CH0 ) ? "blocked" : "enabled",
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(reg50 & CFR_INTR_CH0 ) ? "pending" : "clear ",
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(reg71 & MRDMODE_BLK_CH1 ) ? "blocked" : "enabled",
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(reg57 & ARTTIM23_INTR_CH1) ? "pending" : "clear ");
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return (char *)p;
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}
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@ -176,7 +158,6 @@ static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
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char *p = buffer;
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int i;
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p += sprintf(p, "\n");
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for (i = 0; i < n_cmd_devs; i++) {
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struct pci_dev *dev = cmd_devs[i];
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p = print_cmd64x_get_info(p, dev, i);
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