MIPS: SB1250: Convert IRQ controller lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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f2c194a005
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@ -72,20 +72,20 @@ static struct irq_chip sb1250_irq_type = {
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/* Store the CPU id (not the logical number) */
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int sb1250_irq_owner[SB1250_NR_IRQS];
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static DEFINE_SPINLOCK(sb1250_imr_lock);
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static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);
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void sb1250_mask_irq(int cpu, int irq)
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{
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unsigned long flags;
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u64 cur_ints;
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spin_lock_irqsave(&sb1250_imr_lock, flags);
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raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
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cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
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R_IMR_INTERRUPT_MASK));
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cur_ints |= (((u64) 1) << irq);
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____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
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R_IMR_INTERRUPT_MASK));
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spin_unlock_irqrestore(&sb1250_imr_lock, flags);
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raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
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}
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void sb1250_unmask_irq(int cpu, int irq)
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@ -93,13 +93,13 @@ void sb1250_unmask_irq(int cpu, int irq)
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unsigned long flags;
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u64 cur_ints;
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spin_lock_irqsave(&sb1250_imr_lock, flags);
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raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
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cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
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R_IMR_INTERRUPT_MASK));
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cur_ints &= ~(((u64) 1) << irq);
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____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
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R_IMR_INTERRUPT_MASK));
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spin_unlock_irqrestore(&sb1250_imr_lock, flags);
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raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
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}
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#ifdef CONFIG_SMP
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@ -115,7 +115,7 @@ static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
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cpu = cpu_logical_map(i);
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/* Protect against other affinity changers and IMR manipulation */
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spin_lock_irqsave(&sb1250_imr_lock, flags);
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raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
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/* Swizzle each CPU's IMR (but leave the IP selection alone) */
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old_cpu = sb1250_irq_owner[irq];
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@ -137,7 +137,7 @@ static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
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____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
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R_IMR_INTERRUPT_MASK));
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}
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spin_unlock_irqrestore(&sb1250_imr_lock, flags);
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raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
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return 0;
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}
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