OMAP4: clock data: Remove UNIPRO clock nodes
UNIPRO was removed from OMAP4 devices from ES2.0 onwards. Since this IP was anyway non-functional and not supported, it is best to remove it completely. Signed-off-by: Jon Hunter <jon-hunter@ti.com> [b-cousson@ti.com: Update the changelog] Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: split PRCM header file changes into a separate patch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
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de47453576
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arch/arm/mach-omap2
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@ -935,63 +935,6 @@ static struct clk dpll_per_m7x2_ck = {
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.set_rate = &omap2_clksel_set_rate,
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};
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/* DPLL_UNIPRO */
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static struct dpll_data dpll_unipro_dd = {
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.mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
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.clk_bypass = &sys_clkin_ck,
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.clk_ref = &sys_clkin_ck,
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.control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
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.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
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.autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
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.idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
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.mult_mask = OMAP4430_DPLL_MULT_MASK,
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.div1_mask = OMAP4430_DPLL_DIV_MASK,
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.enable_mask = OMAP4430_DPLL_EN_MASK,
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.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
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.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
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.max_multiplier = 2047,
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.max_divider = 128,
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.min_divider = 1,
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};
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static struct clk dpll_unipro_ck = {
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.name = "dpll_unipro_ck",
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.parent = &sys_clkin_ck,
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.dpll_data = &dpll_unipro_dd,
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.init = &omap2_init_dpll_parent,
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.ops = &clkops_omap3_noncore_dpll_ops,
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.recalc = &omap3_dpll_recalc,
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.round_rate = &omap2_dpll_round_rate,
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.set_rate = &omap3_noncore_dpll_set_rate,
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};
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static struct clk dpll_unipro_x2_ck = {
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.name = "dpll_unipro_x2_ck",
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.parent = &dpll_unipro_ck,
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.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
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.flags = CLOCK_CLKOUTX2,
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.ops = &clkops_omap4_dpllmx_ops,
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.recalc = &omap3_clkoutx2_recalc,
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};
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static const struct clksel dpll_unipro_m2x2_div[] = {
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{ .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
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{ .parent = NULL },
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};
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static struct clk dpll_unipro_m2x2_ck = {
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.name = "dpll_unipro_m2x2_ck",
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.parent = &dpll_unipro_x2_ck,
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.clksel = dpll_unipro_m2x2_div,
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.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
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.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
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.ops = &clkops_omap4_dpllmx_ops,
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.recalc = &omap2_clksel_recalc,
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.round_rate = &omap2_clksel_round_rate,
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.set_rate = &omap2_clksel_set_rate,
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};
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static struct clk usb_hs_clk_div_ck = {
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.name = "usb_hs_clk_div_ck",
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.parent = &dpll_abe_m3x2_ck,
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@ -3058,9 +3001,6 @@ static struct omap_clk omap44xx_clks[] = {
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CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
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CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
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CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
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CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
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CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X),
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CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
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CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
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CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
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CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
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