drm/i915: Do not acquire crtc state to check clock during modeset, v4.
Parallel modesets are still not allowed, but this will allow updating a different crtc during a modeset if the clock is not changed. Additionally when all pipes are DPMS off the cdclk will be lowered to the minimum allowed. Changes since v1: - Add dev_priv->active_crtcs for tracking which crtcs are active. - Rename min_cdclk to min_pixclk and move to dev_priv. - Add a active_crtcs mask which is updated atomically. - Add intel_atomic_state->modeset which is set on modesets. - Commit new pixclk/active_crtcs right after state swap. Changes since v2: - Make the changes related to max_pixel_rate calculations more readable. Changes since v3: - Add cherryview and missing WARN_ON to readout. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com>
This commit is contained in:
Maarten Lankhorst
parent
bf8a0af0cc
commit
565602d750
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@ -1819,8 +1819,13 @@ struct drm_i915_private {
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struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
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#endif
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/* dpll and cdclk state is protected by connection_mutex */
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int num_shared_dpll;
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struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
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unsigned int active_crtcs;
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unsigned int min_pixclk[I915_MAX_PIPES];
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int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
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struct i915_workarounds workarounds;
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@ -308,5 +308,5 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
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{
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struct intel_atomic_state *state = to_intel_atomic_state(s);
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drm_atomic_state_default_clear(&state->base);
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state->dpll_set = false;
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state->dpll_set = state->modeset = false;
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}
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@ -6063,22 +6063,31 @@ static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
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static int intel_mode_max_pixclk(struct drm_device *dev,
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struct drm_atomic_state *state)
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{
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struct intel_crtc *intel_crtc;
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struct intel_crtc_state *crtc_state;
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int max_pixclk = 0;
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struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc;
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struct drm_crtc_state *crtc_state;
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unsigned max_pixclk = 0, i;
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enum pipe pipe;
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for_each_intel_crtc(dev, intel_crtc) {
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crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
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if (IS_ERR(crtc_state))
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return PTR_ERR(crtc_state);
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memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
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sizeof(intel_state->min_pixclk));
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if (!crtc_state->base.enable)
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continue;
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for_each_crtc_in_state(state, crtc, crtc_state, i) {
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int pixclk = 0;
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max_pixclk = max(max_pixclk,
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crtc_state->base.adjusted_mode.crtc_clock);
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if (crtc_state->enable)
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pixclk = crtc_state->adjusted_mode.crtc_clock;
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intel_state->min_pixclk[i] = pixclk;
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}
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if (!intel_state->active_crtcs)
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return 0;
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for_each_pipe(dev_priv, pipe)
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max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
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return max_pixclk;
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}
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@ -6383,6 +6392,9 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
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for_each_power_domain(domain, domains)
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intel_display_power_put(dev_priv, domain);
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intel_crtc->enabled_power_domains = 0;
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dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
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dev_priv->min_pixclk[intel_crtc->pipe] = 0;
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}
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/*
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@ -9679,29 +9691,41 @@ static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
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/* compute the max rate for new configuration */
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static int ilk_max_pixel_rate(struct drm_atomic_state *state)
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{
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struct intel_crtc *intel_crtc;
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struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
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struct drm_i915_private *dev_priv = state->dev->dev_private;
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struct drm_crtc *crtc;
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struct drm_crtc_state *cstate;
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struct intel_crtc_state *crtc_state;
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int max_pixel_rate = 0;
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unsigned max_pixel_rate = 0, i;
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enum pipe pipe;
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for_each_intel_crtc(state->dev, intel_crtc) {
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memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
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sizeof(intel_state->min_pixclk));
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for_each_crtc_in_state(state, crtc, cstate, i) {
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int pixel_rate;
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crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
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if (IS_ERR(crtc_state))
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return PTR_ERR(crtc_state);
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if (!crtc_state->base.enable)
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crtc_state = to_intel_crtc_state(cstate);
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if (!crtc_state->base.enable) {
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intel_state->min_pixclk[i] = 0;
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continue;
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}
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pixel_rate = ilk_pipe_pixel_rate(crtc_state);
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/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
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if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
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if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
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pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
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max_pixel_rate = max(max_pixel_rate, pixel_rate);
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intel_state->min_pixclk[i] = pixel_rate;
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}
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if (!intel_state->active_crtcs)
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return 0;
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for_each_pipe(dev_priv, pipe)
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max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
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return max_pixel_rate;
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}
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@ -13208,15 +13232,27 @@ static int intel_modeset_all_pipes(struct drm_atomic_state *state)
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static int intel_modeset_checks(struct drm_atomic_state *state)
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{
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struct drm_device *dev = state->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret;
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struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
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struct drm_i915_private *dev_priv = state->dev->dev_private;
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struct drm_crtc *crtc;
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struct drm_crtc_state *crtc_state;
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int ret = 0, i;
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if (!check_digital_port_conflicts(state)) {
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DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
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return -EINVAL;
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}
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intel_state->modeset = true;
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intel_state->active_crtcs = dev_priv->active_crtcs;
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for_each_crtc_in_state(state, crtc, crtc_state, i) {
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if (crtc_state->active)
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intel_state->active_crtcs |= 1 << i;
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else
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intel_state->active_crtcs &= ~(1 << i);
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}
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/*
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* See if the config requires any additional preparation, e.g.
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* to adjust global state with pipes off. We need to do this
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@ -13240,7 +13276,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
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intel_modeset_clear_plls(state);
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if (IS_HASWELL(dev))
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if (IS_HASWELL(dev_priv))
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return haswell_mode_set_planes_workaround(state);
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return 0;
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@ -13458,12 +13494,12 @@ static int intel_atomic_commit(struct drm_device *dev,
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struct drm_atomic_state *state,
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bool async)
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{
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struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc_state *crtc_state;
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struct drm_crtc *crtc;
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int ret = 0;
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int i;
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bool any_ms = false;
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int ret = 0, i;
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bool hw_check = intel_state->modeset;
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ret = intel_atomic_prepare_commit(dev, state, async);
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if (ret) {
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@ -13474,13 +13510,18 @@ static int intel_atomic_commit(struct drm_device *dev,
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drm_atomic_helper_swap_state(dev, state);
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dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
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if (intel_state->modeset) {
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memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
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sizeof(intel_state->min_pixclk));
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dev_priv->active_crtcs = intel_state->active_crtcs;
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}
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for_each_crtc_in_state(state, crtc, crtc_state, i) {
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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if (!needs_modeset(crtc->state))
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continue;
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any_ms = true;
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intel_pre_plane_update(intel_crtc);
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if (crtc_state->active) {
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@ -13505,7 +13546,7 @@ static int intel_atomic_commit(struct drm_device *dev,
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* update the the output configuration. */
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intel_modeset_update_crtc_state(state);
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if (any_ms) {
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if (intel_state->modeset) {
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intel_shared_dpll_commit(state);
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drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
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@ -13532,7 +13573,7 @@ static int intel_atomic_commit(struct drm_device *dev,
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put_domains = modeset_get_crtc_power_domains(crtc);
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/* make sure intel_modeset_check_state runs */
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any_ms = true;
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hw_check = true;
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}
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if (!modeset)
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@ -13559,7 +13600,7 @@ static int intel_atomic_commit(struct drm_device *dev,
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drm_atomic_helper_cleanup_planes(dev, state);
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mutex_unlock(&dev->struct_mutex);
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if (any_ms)
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if (hw_check)
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intel_modeset_check_state(dev, state);
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drm_atomic_state_free(state);
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@ -15591,16 +15632,40 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
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struct intel_connector *connector;
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int i;
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dev_priv->active_crtcs = 0;
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for_each_intel_crtc(dev, crtc) {
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__drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
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memset(crtc->config, 0, sizeof(*crtc->config));
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crtc->config->base.crtc = &crtc->base;
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struct intel_crtc_state *crtc_state = crtc->config;
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int pixclk = 0;
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crtc->active = dev_priv->display.get_pipe_config(crtc,
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crtc->config);
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__drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
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memset(crtc_state, 0, sizeof(*crtc_state));
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crtc_state->base.crtc = &crtc->base;
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crtc->base.state->active = crtc->active;
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crtc->base.enabled = crtc->active;
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crtc_state->base.active = crtc_state->base.enable =
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dev_priv->display.get_pipe_config(crtc, crtc_state);
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crtc->base.enabled = crtc_state->base.enable;
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crtc->active = crtc_state->base.active;
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if (crtc_state->base.active) {
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dev_priv->active_crtcs |= 1 << crtc->pipe;
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if (IS_BROADWELL(dev_priv)) {
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pixclk = ilk_pipe_pixel_rate(crtc_state);
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/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
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if (crtc_state->ips_enabled)
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pixclk = DIV_ROUND_UP(pixclk * 100, 95);
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} else if (IS_VALLEYVIEW(dev_priv) ||
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IS_CHERRYVIEW(dev_priv) ||
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IS_BROXTON(dev_priv))
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pixclk = crtc_state->base.adjusted_mode.crtc_clock;
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else
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WARN_ON(dev_priv->display.modeset_calc_cdclk);
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}
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dev_priv->min_pixclk[crtc->pipe] = pixclk;
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readout_plane_state(crtc);
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@ -246,7 +246,12 @@ struct intel_atomic_state {
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struct drm_atomic_state base;
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unsigned int cdclk;
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bool dpll_set;
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bool dpll_set, modeset;
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unsigned int active_crtcs;
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unsigned int min_pixclk[I915_MAX_PIPES];
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struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
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struct intel_wm_config wm_config;
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};
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