Blackfin arch: Add Support for Peripheral PortMux and resouce allocation
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Michael Hennerich
Bryan Wu
parent
520473b077
commit
5610db61cf
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@ -31,38 +31,64 @@
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#include <linux/err.h>
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#include <asm/blackfin.h>
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#include <asm/gpio.h>
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#include <asm/portmux.h>
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#include <linux/irq.h>
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static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
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(struct gpio_port_t *) PORTA_FER,
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(struct gpio_port_t *) PORTB_FER,
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(struct gpio_port_t *) PORTC_FER,
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(struct gpio_port_t *) PORTD_FER,
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(struct gpio_port_t *) PORTE_FER,
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(struct gpio_port_t *) PORTF_FER,
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(struct gpio_port_t *) PORTG_FER,
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(struct gpio_port_t *) PORTH_FER,
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(struct gpio_port_t *) PORTI_FER,
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(struct gpio_port_t *) PORTJ_FER,
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(struct gpio_port_t *)PORTA_FER,
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(struct gpio_port_t *)PORTB_FER,
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(struct gpio_port_t *)PORTC_FER,
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(struct gpio_port_t *)PORTD_FER,
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(struct gpio_port_t *)PORTE_FER,
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(struct gpio_port_t *)PORTF_FER,
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(struct gpio_port_t *)PORTG_FER,
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(struct gpio_port_t *)PORTH_FER,
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(struct gpio_port_t *)PORTI_FER,
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(struct gpio_port_t *)PORTJ_FER,
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};
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static unsigned short reserved_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
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static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
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static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
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inline int check_gpio(unsigned short gpio)
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{
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if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 \
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|| gpio == GPIO_PH14 || gpio == GPIO_PH15 \
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|| gpio == GPIO_PJ14 || gpio == GPIO_PJ15 \
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|| gpio > MAX_BLACKFIN_GPIOS)
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if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
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|| gpio == GPIO_PH14 || gpio == GPIO_PH15
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|| gpio == GPIO_PJ14 || gpio == GPIO_PJ15
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|| gpio > MAX_BLACKFIN_GPIOS)
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return -EINVAL;
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return 0;
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}
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inline void portmux_setup(unsigned short portno, unsigned short function)
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{
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u32 pmux;
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pmux = gpio_array[gpio_bank(portno)]->port_mux;
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pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
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pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
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gpio_array[gpio_bank(portno)]->port_mux = pmux;
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}
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inline u16 get_portmux(unsigned short portno)
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{
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u32 pmux;
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pmux = gpio_array[gpio_bank(portno)]->port_mux;
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return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
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}
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static void port_setup(unsigned short gpio, unsigned short usage)
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{
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if (usage == GPIO_USAGE) {
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if (gpio_array[gpio_bank(gpio)]->port_fer & gpio_bit(gpio))
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printk(KERN_WARNING "bfin-gpio: Possible Conflict with Peripheral "
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printk(KERN_WARNING
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"bfin-gpio: Possible Conflict with Peripheral "
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"usage and GPIO %d detected!\n", gpio);
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gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
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} else
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@ -72,18 +98,116 @@ static void port_setup(unsigned short gpio, unsigned short usage)
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static int __init bfin_gpio_init(void)
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{
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int i;
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printk(KERN_INFO "Blackfin GPIO Controller\n");
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for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE)
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reserved_map[gpio_bank(i)] = 0;
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return 0;
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}
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arch_initcall(bfin_gpio_init);
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int peripheral_request(unsigned short per, const char *label)
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{
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unsigned long flags;
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unsigned short ident = P_IDENT(per);
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if (!(per & P_DEFINED))
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return -ENODEV;
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if (check_gpio(ident) < 0)
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return -EINVAL;
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local_irq_save(flags);
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if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
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printk(KERN_ERR
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"%s: Peripheral %d is already reserved as GPIO!\n",
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__FUNCTION__, per);
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dump_stack();
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local_irq_restore(flags);
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return -EBUSY;
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}
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if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
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u16 funct = get_portmux(ident);
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if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
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printk(KERN_ERR
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"%s: Peripheral %d is already reserved!\n",
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__FUNCTION__, per);
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dump_stack();
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local_irq_restore(flags);
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return -EBUSY;
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}
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}
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reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
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portmux_setup(ident, P_FUNCT2MUX(per));
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port_setup(ident, PERIPHERAL_USAGE);
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(peripheral_request);
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int peripheral_request_list(unsigned short per[], const char *label)
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{
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u16 cnt;
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int ret;
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for (cnt = 0; per[cnt] != 0; cnt++) {
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ret = peripheral_request(per[cnt], label);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL(peripheral_request_list);
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void peripheral_free(unsigned short per)
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{
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unsigned long flags;
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unsigned short ident = P_IDENT(per);
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if (!(per & P_DEFINED))
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return;
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if (check_gpio(ident) < 0)
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return;
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local_irq_save(flags);
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if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
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printk(KERN_ERR "bfin-gpio: Peripheral %d wasn't reserved!\n", per);
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dump_stack();
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local_irq_restore(flags);
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return;
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}
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if (!(per & P_MAYSHARE)) {
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port_setup(ident, GPIO_USAGE);
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}
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reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL(peripheral_free);
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void peripheral_free_list(unsigned short per[])
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{
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u16 cnt;
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for (cnt = 0; per[cnt] != 0; cnt++) {
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peripheral_free(per[cnt]);
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}
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}
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EXPORT_SYMBOL(peripheral_free_list);
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/***********************************************************
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*
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@ -109,13 +233,22 @@ int gpio_request(unsigned short gpio, const char *label)
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local_irq_save(flags);
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if (unlikely(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
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if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
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printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved!\n", gpio);
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dump_stack();
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local_irq_restore(flags);
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return -EBUSY;
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}
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reserved_map[gpio_bank(gpio)] |= gpio_bit(gpio);
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if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
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printk(KERN_ERR
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"bfin-gpio: GPIO %d is already reserved as Peripheral!\n", gpio);
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dump_stack();
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local_irq_restore(flags);
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return -EBUSY;
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}
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reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
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local_irq_restore(flags);
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@ -125,7 +258,6 @@ int gpio_request(unsigned short gpio, const char *label)
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}
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EXPORT_SYMBOL(gpio_request);
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void gpio_free(unsigned short gpio)
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{
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unsigned long flags;
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@ -135,25 +267,24 @@ void gpio_free(unsigned short gpio)
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local_irq_save(flags);
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if (unlikely(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
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if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
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printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio);
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dump_stack();
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local_irq_restore(flags);
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return;
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}
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reserved_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
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reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL(gpio_free);
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void gpio_direction_input(unsigned short gpio)
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{
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unsigned long flags;
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BUG_ON(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)));
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BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
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local_irq_save(flags);
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gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
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@ -166,7 +297,7 @@ void gpio_direction_output(unsigned short gpio)
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{
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unsigned long flags;
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BUG_ON(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)));
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BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
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local_irq_save(flags);
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gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
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@ -210,6 +210,56 @@
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#ifdef BF561_FAMILY
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#define MAX_BLACKFIN_GPIOS 48
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#define GPIO_PF0 0
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#define GPIO_PF1 1
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#define GPIO_PF2 2
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#define GPIO_PF3 3
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#define GPIO_PF4 4
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#define GPIO_PF5 5
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#define GPIO_PF6 6
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#define GPIO_PF7 7
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#define GPIO_PF8 8
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#define GPIO_PF9 9
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#define GPIO_PF10 10
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#define GPIO_PF11 11
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#define GPIO_PF12 12
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#define GPIO_PF13 13
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#define GPIO_PF14 14
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#define GPIO_PF15 15
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#define GPIO_PF16 16
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#define GPIO_PF17 17
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#define GPIO_PF18 18
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#define GPIO_PF19 19
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#define GPIO_PF20 20
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#define GPIO_PF21 21
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#define GPIO_PF22 22
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#define GPIO_PF23 23
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#define GPIO_PF24 24
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#define GPIO_PF25 25
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#define GPIO_PF26 26
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#define GPIO_PF27 27
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#define GPIO_PF28 28
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#define GPIO_PF29 29
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#define GPIO_PF30 30
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#define GPIO_PF31 31
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#define GPIO_PF32 32
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#define GPIO_PF33 33
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#define GPIO_PF34 34
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#define GPIO_PF35 35
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#define GPIO_PF36 36
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#define GPIO_PF37 37
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#define GPIO_PF38 38
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#define GPIO_PF39 39
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#define GPIO_PF40 40
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#define GPIO_PF41 41
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#define GPIO_PF42 42
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#define GPIO_PF43 43
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#define GPIO_PF44 44
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#define GPIO_PF45 45
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#define GPIO_PF46 46
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#define GPIO_PF47 47
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#define PORT_FIO0 GPIO_0
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#define PORT_FIO1 GPIO_16
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#define PORT_FIO2 GPIO_32
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@ -0,0 +1,65 @@
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#ifndef _MACH_PORTMUX_H_
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#define _MACH_PORTMUX_H_
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#define P_PPI0_CLK (P_DONTCARE)
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#define P_PPI0_FS1 (P_DONTCARE)
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#define P_PPI0_FS2 (P_DONTCARE)
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#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
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#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
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#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
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#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
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#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
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#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
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#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
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#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
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#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
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#define P_PPI0_D0 (P_DONTCARE)
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#define P_PPI0_D1 (P_DONTCARE)
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#define P_PPI0_D2 (P_DONTCARE)
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#define P_PPI0_D3 (P_DONTCARE)
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#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
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#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
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#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
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#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
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#define P_SPORT1_TSCLK (P_DONTCARE)
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#define P_SPORT1_RSCLK (P_DONTCARE)
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#define P_SPORT0_TSCLK (P_DONTCARE)
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#define P_SPORT0_RSCLK (P_DONTCARE)
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#define P_UART0_RX (P_DONTCARE)
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#define P_UART0_TX (P_DONTCARE)
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#define P_SPORT1_DRSEC (P_DONTCARE)
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#define P_SPORT1_RFS (P_DONTCARE)
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#define P_SPORT1_DTPRI (P_DONTCARE)
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#define P_SPORT1_DTSEC (P_DONTCARE)
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#define P_SPORT1_TFS (P_DONTCARE)
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#define P_SPORT1_DRPRI (P_DONTCARE)
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#define P_SPORT0_DRSEC (P_DONTCARE)
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#define P_SPORT0_RFS (P_DONTCARE)
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#define P_SPORT0_DTPRI (P_DONTCARE)
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#define P_SPORT0_DTSEC (P_DONTCARE)
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#define P_SPORT0_TFS (P_DONTCARE)
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#define P_SPORT0_DRPRI (P_DONTCARE)
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#define P_SPI0_MOSI (P_DONTCARE)
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#define P_SPI0_MIS0 (P_DONTCARE)
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#define P_SPI0_SCK (P_DONTCARE)
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#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
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#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
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#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
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#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
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#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
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#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
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#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
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#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
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#define P_TMR2 (P_DONTCARE)
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#define P_TMR1 (P_DONTCARE)
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#define P_TMR0 (P_DONTCARE)
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#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1))
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#endif /* _MACH_PORTMUX_H_ */
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@ -0,0 +1,109 @@
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#ifndef _MACH_PORTMUX_H_
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#define _MACH_PORTMUX_H_
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#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
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#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
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#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
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#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
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#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
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#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
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#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
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#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
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#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
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#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
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#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
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#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
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#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
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#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
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#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
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#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
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#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
|
||||
#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
|
||||
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
|
||||
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
|
||||
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
|
||||
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
|
||||
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
|
||||
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
|
||||
#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
|
||||
#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
|
||||
#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
|
||||
#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
|
||||
|
||||
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
|
||||
#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
|
||||
#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
|
||||
#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
|
||||
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
|
||||
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
|
||||
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
|
||||
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
|
||||
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
|
||||
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
|
||||
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
|
||||
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
|
||||
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
|
||||
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
|
||||
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
|
||||
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
|
||||
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
|
||||
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
|
||||
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
|
||||
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
|
||||
#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
|
||||
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
|
||||
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
|
||||
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
|
||||
|
||||
#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
|
||||
#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
|
||||
#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
|
||||
#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
|
||||
#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
|
||||
#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
|
||||
#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
|
||||
#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
|
||||
#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
|
||||
#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
|
||||
#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
|
||||
#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
|
||||
#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
|
||||
#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
|
||||
#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
|
||||
#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
|
||||
#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
|
||||
#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
|
||||
#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
|
||||
|
||||
#define PORT_PJ0 (GPIO_PH15 + 1)
|
||||
#define PORT_PJ1 (GPIO_PH15 + 2)
|
||||
#define PORT_PJ2 (GPIO_PH15 + 3)
|
||||
#define PORT_PJ3 (GPIO_PH15 + 4)
|
||||
#define PORT_PJ4 (GPIO_PH15 + 5)
|
||||
#define PORT_PJ5 (GPIO_PH15 + 6)
|
||||
#define PORT_PJ6 (GPIO_PH15 + 7)
|
||||
#define PORT_PJ7 (GPIO_PH15 + 8)
|
||||
#define PORT_PJ8 (GPIO_PH15 + 9)
|
||||
#define PORT_PJ9 (GPIO_PH15 + 10)
|
||||
#define PORT_PJ10 (GPIO_PH15 + 11)
|
||||
#define PORT_PJ11 (GPIO_PH15 + 12)
|
||||
|
||||
#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
|
||||
#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
|
||||
#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
|
||||
#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
|
||||
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
|
||||
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
|
||||
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
|
||||
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
|
||||
#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
|
||||
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
|
||||
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
|
||||
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
|
||||
#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
|
||||
#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
|
||||
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
|
||||
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
|
||||
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
|
||||
|
||||
#endif /* _MACH_PORTMUX_H_ */
|
||||
|
|
@ -0,0 +1,270 @@
|
|||
#ifndef _MACH_PORTMUX_H_
|
||||
#define _MACH_PORTMUX_H_
|
||||
|
||||
#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
|
||||
#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
|
||||
#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
|
||||
#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
|
||||
#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
|
||||
#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
|
||||
#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
|
||||
#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
|
||||
#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
|
||||
#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
|
||||
#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
|
||||
#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
|
||||
#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
|
||||
#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
|
||||
#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
|
||||
#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
|
||||
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
|
||||
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
|
||||
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
|
||||
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
|
||||
|
||||
#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
|
||||
#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
|
||||
#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
|
||||
#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
|
||||
#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
|
||||
#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
|
||||
#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
|
||||
#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
|
||||
#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
|
||||
#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
|
||||
#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
|
||||
#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
|
||||
#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
|
||||
#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
|
||||
#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
|
||||
#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
|
||||
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
|
||||
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
|
||||
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
|
||||
|
||||
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
|
||||
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
|
||||
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
|
||||
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
|
||||
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
|
||||
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
|
||||
#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
|
||||
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
|
||||
#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
|
||||
#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
|
||||
#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
|
||||
#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
|
||||
#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
|
||||
#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
|
||||
#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
|
||||
#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
|
||||
|
||||
#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
|
||||
#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
|
||||
#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
|
||||
#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
|
||||
#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
|
||||
#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
|
||||
#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
|
||||
#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
|
||||
#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
|
||||
#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
|
||||
#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
|
||||
#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
|
||||
#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
|
||||
#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
|
||||
#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
|
||||
#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
|
||||
|
||||
#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
|
||||
#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
|
||||
#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
|
||||
#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
|
||||
#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
|
||||
#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
|
||||
#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
|
||||
#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
|
||||
#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
|
||||
#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
|
||||
#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
|
||||
#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
|
||||
#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
|
||||
#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
|
||||
#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
|
||||
#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
|
||||
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
|
||||
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
|
||||
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
|
||||
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
|
||||
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
|
||||
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
|
||||
#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
|
||||
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
|
||||
#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
|
||||
#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
|
||||
#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
|
||||
#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
|
||||
#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
|
||||
#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
|
||||
#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
|
||||
#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
|
||||
#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
|
||||
#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
|
||||
#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
|
||||
#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
|
||||
#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
|
||||
#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
|
||||
#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
|
||||
#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
|
||||
#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
|
||||
#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
|
||||
#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
|
||||
#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
|
||||
#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
|
||||
#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
|
||||
|
||||
#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
|
||||
#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
|
||||
#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
|
||||
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
|
||||
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
|
||||
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
|
||||
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
|
||||
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
|
||||
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
|
||||
#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
|
||||
#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
|
||||
#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
|
||||
#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
|
||||
#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
|
||||
#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
|
||||
#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
|
||||
#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
|
||||
#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
|
||||
#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
|
||||
#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
|
||||
#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
|
||||
#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
|
||||
#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
|
||||
#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
|
||||
|
||||
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
|
||||
#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
|
||||
#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
|
||||
#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
|
||||
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
|
||||
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
|
||||
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
|
||||
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
|
||||
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
|
||||
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
|
||||
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
|
||||
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
|
||||
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
|
||||
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
|
||||
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
|
||||
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
|
||||
#define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
|
||||
#define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
|
||||
#define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
|
||||
#define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
|
||||
#define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
|
||||
#define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
|
||||
#define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
|
||||
#define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
|
||||
#define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
|
||||
#define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
|
||||
#define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
|
||||
#define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
|
||||
#define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
|
||||
#define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
|
||||
#define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
|
||||
#define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
|
||||
|
||||
#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
|
||||
#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
|
||||
#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
|
||||
#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
|
||||
#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
|
||||
#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
|
||||
#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
|
||||
#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
|
||||
#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
|
||||
#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
|
||||
#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
|
||||
#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
|
||||
#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
|
||||
#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
|
||||
#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
|
||||
#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
|
||||
#define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
|
||||
#define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
|
||||
#define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
|
||||
#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
|
||||
#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
|
||||
#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
|
||||
#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
|
||||
#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
|
||||
#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
|
||||
#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
|
||||
#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
|
||||
|
||||
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
|
||||
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
|
||||
#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
|
||||
#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
|
||||
#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
|
||||
#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
|
||||
#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
|
||||
#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
|
||||
#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
|
||||
#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
|
||||
#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
|
||||
#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
|
||||
#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
|
||||
#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
|
||||
#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
|
||||
#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
|
||||
#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
|
||||
#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
|
||||
#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
|
||||
#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
|
||||
#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
|
||||
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
|
||||
#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
|
||||
#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
|
||||
|
||||
#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
|
||||
#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
|
||||
#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
|
||||
#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
|
||||
#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
|
||||
#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
|
||||
#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
|
||||
#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
|
||||
#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
|
||||
#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
|
||||
#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
|
||||
#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
|
||||
#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
|
||||
#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
|
||||
#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
|
||||
#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
|
||||
#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
|
||||
|
||||
#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
|
||||
#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
|
||||
#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
|
||||
#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
|
||||
#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
|
||||
#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
|
||||
#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
|
||||
#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
|
||||
#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
|
||||
#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
|
||||
#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
|
||||
#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
|
||||
#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
|
||||
#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
|
||||
|
||||
#endif /* _MACH_PORTMUX_H_ */
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
#ifndef _MACH_PORTMUX_H_
|
||||
#define _MACH_PORTMUX_H_
|
||||
|
||||
#define P_PPI0_CLK (P_DONTCARE)
|
||||
#define P_PPI0_FS1 (P_DONTCARE)
|
||||
#define P_PPI0_FS2 (P_DONTCARE)
|
||||
#define P_PPI0_FS3 (P_DONTCARE)
|
||||
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
|
||||
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
|
||||
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
|
||||
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
|
||||
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
|
||||
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
|
||||
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
|
||||
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
|
||||
#define P_PPI0_D0 (P_DONTCARE)
|
||||
#define P_PPI0_D1 (P_DONTCARE)
|
||||
#define P_PPI0_D2 (P_DONTCARE)
|
||||
#define P_PPI0_D3 (P_DONTCARE)
|
||||
#define P_PPI0_D4 (P_DONTCARE)
|
||||
#define P_PPI0_D5 (P_DONTCARE)
|
||||
#define P_PPI0_D6 (P_DONTCARE)
|
||||
#define P_PPI0_D7 (P_DONTCARE)
|
||||
#define P_PPI1_CLK (P_DONTCARE)
|
||||
#define P_PPI1_FS1 (P_DONTCARE)
|
||||
#define P_PPI1_FS2 (P_DONTCARE)
|
||||
#define P_PPI1_FS3 (P_DONTCARE)
|
||||
#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
|
||||
#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
|
||||
#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
|
||||
#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
|
||||
#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
|
||||
#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
|
||||
#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
|
||||
#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
|
||||
#define P_PPI1_D0 (P_DONTCARE)
|
||||
#define P_PPI1_D1 (P_DONTCARE)
|
||||
#define P_PPI1_D2 (P_DONTCARE)
|
||||
#define P_PPI1_D3 (P_DONTCARE)
|
||||
#define P_PPI1_D4 (P_DONTCARE)
|
||||
#define P_PPI1_D5 (P_DONTCARE)
|
||||
#define P_PPI1_D6 (P_DONTCARE)
|
||||
#define P_PPI1_D7 (P_DONTCARE)
|
||||
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
|
||||
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
|
||||
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
|
||||
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
|
||||
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
|
||||
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
|
||||
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
|
||||
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
|
||||
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
|
||||
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
|
||||
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
|
||||
#define P_SPORT1_DRPRI (P_DONTCARE)
|
||||
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
|
||||
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
|
||||
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
|
||||
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
|
||||
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
|
||||
#define P_SPORT0_DRPRI (P_DONTCARE)
|
||||
#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
|
||||
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
|
||||
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
|
||||
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
|
||||
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
|
||||
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
|
||||
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
|
||||
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
|
||||
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
|
||||
#define P_TMR11 (P_DONTCARE)
|
||||
#define P_TMR10 (P_DONTCARE)
|
||||
#define P_TMR9 (P_DONTCARE)
|
||||
#define P_TMR8 (P_DONTCARE)
|
||||
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
|
||||
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
|
||||
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
|
||||
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
|
||||
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
|
||||
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
|
||||
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
|
||||
#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
|
||||
#define P_SPI0_MOSI (P_DONTCARE)
|
||||
#define P_SPI0_MIS0 (P_DONTCARE)
|
||||
#define P_SPI0_SCK (P_DONTCARE)
|
||||
|
||||
#endif /* _MACH_PORTMUX_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue