[PATCH] ppc32: handle access to non-present IO ports on 8xx
This adds exception table entries for I/O instructions on and changes MachineCheckException() slightly to cover 8xx specifics (on 8xx the MCE can be generated while executing the IO access instruction itself, which is not the case on PowerMac's, as the comment on traps.c details). Signed-off-by: Marcelo Tosatti <marcelo.tosatti@cyclades.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Marcelo Tosatti
Paul Mackerras
parent
c6d95044a2
commit
55b6332ec8
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@ -25,6 +25,11 @@
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#ifdef CONFIG_8xx
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#define ISYNC_8xx isync
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#else
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#define ISYNC_8xx
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#endif
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.text
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.align 5
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@ -800,8 +805,18 @@ _GLOBAL(_insb)
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subi r4,r4,1
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blelr-
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00: lbz r5,0(r3)
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eieio
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stbu r5,1(r4)
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01: eieio
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02: stbu r5,1(r4)
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ISYNC_8xx
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.section .fixup,"ax"
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03: blr
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.text
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.section __ex_table, "a"
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.align 2
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.long 00b, 03b
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.long 01b, 03b
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.long 02b, 03b
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.text
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bdnz 00b
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blr
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@ -811,8 +826,18 @@ _GLOBAL(_outsb)
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subi r4,r4,1
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blelr-
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00: lbzu r5,1(r4)
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stb r5,0(r3)
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eieio
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01: stb r5,0(r3)
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02: eieio
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ISYNC_8xx
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.section .fixup,"ax"
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03: blr
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.text
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.section __ex_table, "a"
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.align 2
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.long 00b, 03b
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.long 01b, 03b
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.long 02b, 03b
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.text
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bdnz 00b
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blr
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@ -822,8 +847,18 @@ _GLOBAL(_insw)
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subi r4,r4,2
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blelr-
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00: lhbrx r5,0,r3
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eieio
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sthu r5,2(r4)
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01: eieio
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02: sthu r5,2(r4)
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ISYNC_8xx
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.section .fixup,"ax"
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03: blr
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.text
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.section __ex_table, "a"
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.align 2
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.long 00b, 03b
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.long 01b, 03b
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.long 02b, 03b
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.text
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bdnz 00b
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blr
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@ -833,8 +868,18 @@ _GLOBAL(_outsw)
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subi r4,r4,2
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blelr-
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00: lhzu r5,2(r4)
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eieio
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sthbrx r5,0,r3
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01: eieio
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02: sthbrx r5,0,r3
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ISYNC_8xx
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.section .fixup,"ax"
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03: blr
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.text
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.section __ex_table, "a"
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.align 2
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.long 00b, 03b
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.long 01b, 03b
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.long 02b, 03b
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.text
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bdnz 00b
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blr
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@ -844,8 +889,18 @@ _GLOBAL(_insl)
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subi r4,r4,4
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blelr-
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00: lwbrx r5,0,r3
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eieio
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stwu r5,4(r4)
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01: eieio
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02: stwu r5,4(r4)
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ISYNC_8xx
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.section .fixup,"ax"
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03: blr
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.text
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.section __ex_table, "a"
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.align 2
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.long 00b, 03b
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.long 01b, 03b
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.long 02b, 03b
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.text
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bdnz 00b
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blr
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@ -855,8 +910,18 @@ _GLOBAL(_outsl)
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subi r4,r4,4
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blelr-
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00: lwzu r5,4(r4)
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stwbrx r5,0,r3
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eieio
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01: stwbrx r5,0,r3
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02: eieio
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ISYNC_8xx
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.section .fixup,"ax"
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03: blr
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.text
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.section __ex_table, "a"
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.align 2
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.long 00b, 03b
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.long 01b, 03b
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.long 02b, 03b
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.text
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bdnz 00b
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blr
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@ -867,8 +932,18 @@ _GLOBAL(_insw_ns)
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subi r4,r4,2
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blelr-
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00: lhz r5,0(r3)
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eieio
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sthu r5,2(r4)
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01: eieio
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02: sthu r5,2(r4)
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ISYNC_8xx
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.section .fixup,"ax"
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03: blr
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.text
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.section __ex_table, "a"
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.align 2
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.long 00b, 03b
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.long 01b, 03b
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.long 02b, 03b
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.text
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bdnz 00b
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blr
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@ -879,8 +954,18 @@ _GLOBAL(_outsw_ns)
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subi r4,r4,2
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blelr-
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00: lhzu r5,2(r4)
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sth r5,0(r3)
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eieio
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01: sth r5,0(r3)
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02: eieio
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ISYNC_8xx
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.section .fixup,"ax"
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03: blr
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.text
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.section __ex_table, "a"
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.align 2
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.long 00b, 03b
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.long 01b, 03b
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.long 02b, 03b
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.text
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bdnz 00b
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blr
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@ -891,8 +976,18 @@ _GLOBAL(_insl_ns)
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subi r4,r4,4
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blelr-
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00: lwz r5,0(r3)
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eieio
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stwu r5,4(r4)
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01: eieio
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02: stwu r5,4(r4)
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ISYNC_8xx
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.section .fixup,"ax"
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03: blr
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.text
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.section __ex_table, "a"
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.align 2
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.long 00b, 03b
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.long 01b, 03b
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.long 02b, 03b
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.text
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bdnz 00b
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blr
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@ -903,8 +998,18 @@ _GLOBAL(_outsl_ns)
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subi r4,r4,4
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blelr-
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00: lwzu r5,4(r4)
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stw r5,0(r3)
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eieio
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01: stw r5,0(r3)
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02: eieio
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ISYNC_8xx
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.section .fixup,"ax"
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03: blr
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.text
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.section __ex_table, "a"
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.align 2
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.long 00b, 03b
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.long 01b, 03b
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.long 02b, 03b
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.text
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bdnz 00b
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blr
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@ -159,7 +159,7 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
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*/
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static inline int check_io_access(struct pt_regs *regs)
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{
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#ifdef CONFIG_PPC_PMAC
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#if defined CONFIG_PPC_PMAC || defined CONFIG_8xx
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unsigned long msr = regs->msr;
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const struct exception_table_entry *entry;
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unsigned int *nip = (unsigned int *)regs->nip;
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@ -178,7 +178,11 @@ static inline int check_io_access(struct pt_regs *regs)
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nip -= 2;
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else if (*nip == 0x4c00012c) /* isync */
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--nip;
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if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
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/* eieio from I/O string functions */
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else if ((*nip) == 0x7c0006ac || *(nip+1) == 0x7c0006ac)
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nip += 2;
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if (*nip == 0x7c0004ac || (*nip >> 26) == 3 ||
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(*(nip+1) >> 26) == 3) {
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/* sync or twi */
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unsigned int rb;
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@ -237,9 +237,9 @@ static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
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#define outsl(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
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/*
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* On powermacs, we will get a machine check exception if we
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* try to read data from a non-existent I/O port. Because the
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* machine check is an asynchronous exception, it isn't
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* On powermacs and 8xx we will get a machine check exception
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* if we try to read data from a non-existent I/O port. Because
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* the machine check is an asynchronous exception, it isn't
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* well-defined which instruction SRR0 will point to when the
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* exception occurs.
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* With the sequence below (twi; isync; nop), we have found that
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@ -258,7 +258,7 @@ extern __inline__ unsigned int name(unsigned int port) \
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{ \
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unsigned int x; \
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__asm__ __volatile__( \
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op " %0,0,%1\n" \
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"0:" op " %0,0,%1\n" \
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"1: twi 0,%0,0\n" \
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"2: isync\n" \
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"3: nop\n" \
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@ -269,6 +269,7 @@ extern __inline__ unsigned int name(unsigned int port) \
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".previous\n" \
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".section __ex_table,\"a\"\n" \
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" .align 2\n" \
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" .long 0b,5b\n" \
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" .long 1b,5b\n" \
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" .long 2b,5b\n" \
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" .long 3b,5b\n" \
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@ -282,11 +283,12 @@ extern __inline__ unsigned int name(unsigned int port) \
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extern __inline__ void name(unsigned int val, unsigned int port) \
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{ \
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__asm__ __volatile__( \
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op " %0,0,%1\n" \
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"0:" op " %0,0,%1\n" \
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"1: sync\n" \
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"2:\n" \
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".section __ex_table,\"a\"\n" \
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" .align 2\n" \
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" .long 0b,2b\n" \
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" .long 1b,2b\n" \
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".previous" \
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: : "r" (val), "r" (port + ___IO_BASE)); \
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