ALSA: pcxhr - add support for gpio ports and minor bug fix
- add support for gpio ports (2 GPI, 2 GPO) of pcxhr stereo cards - minor bugfixes : allow setting clock to internal by the mixer even if there is no stream (but monitoring) Signed-off-by: Markus Bollinger <bollinger@digigram.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
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55aef45085
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@ -1334,6 +1334,40 @@ static void pcxhr_proc_sync(struct snd_info_entry *entry,
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snd_iprintf(buffer, "\n");
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}
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static void pcxhr_proc_gpio_read(struct snd_info_entry *entry,
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struct snd_info_buffer *buffer)
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{
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struct snd_pcxhr *chip = entry->private_data;
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struct pcxhr_mgr *mgr = chip->mgr;
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/* commands available when embedded DSP is running */
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if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
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/* gpio ports on stereo boards only available */
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int value = 0;
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hr222_read_gpio(mgr, 1, &value); /* GPI */
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snd_iprintf(buffer, "GPI: 0x%x\n", value);
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hr222_read_gpio(mgr, 0, &value); /* GP0 */
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snd_iprintf(buffer, "GPO: 0x%x\n", value);
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} else
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snd_iprintf(buffer, "no firmware loaded\n");
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snd_iprintf(buffer, "\n");
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}
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static void pcxhr_proc_gpo_write(struct snd_info_entry *entry,
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struct snd_info_buffer *buffer)
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{
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struct snd_pcxhr *chip = entry->private_data;
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struct pcxhr_mgr *mgr = chip->mgr;
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char line[64];
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int value;
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/* commands available when embedded DSP is running */
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if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)))
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return;
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while (!snd_info_get_line(buffer, line, sizeof(line))) {
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if (sscanf(line, "GPO: 0x%x", &value) != 1)
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continue;
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hr222_write_gpo(mgr, value); /* GP0 */
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}
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}
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static void __devinit pcxhr_proc_init(struct snd_pcxhr *chip)
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{
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struct snd_info_entry *entry;
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@ -1342,6 +1376,13 @@ static void __devinit pcxhr_proc_init(struct snd_pcxhr *chip)
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snd_info_set_text_ops(entry, chip, pcxhr_proc_info);
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if (! snd_card_proc_new(chip->card, "sync", &entry))
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snd_info_set_text_ops(entry, chip, pcxhr_proc_sync);
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/* gpio available on stereo sound cards only */
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if (chip->mgr->is_hr_stereo &&
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!snd_card_proc_new(chip->card, "gpio", &entry)) {
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snd_info_set_text_ops(entry, chip, pcxhr_proc_gpio_read);
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entry->c.text.write = pcxhr_proc_gpo_write;
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entry->mode |= S_IWUSR;
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}
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}
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/* end of proc interface */
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@ -27,8 +27,8 @@
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#include <linux/mutex.h>
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#include <sound/pcm.h>
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#define PCXHR_DRIVER_VERSION 0x000905 /* 0.9.5 */
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#define PCXHR_DRIVER_VERSION_STRING "0.9.5" /* 0.9.5 */
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#define PCXHR_DRIVER_VERSION 0x000906 /* 0.9.6 */
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#define PCXHR_DRIVER_VERSION_STRING "0.9.6" /* 0.9.6 */
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#define PCXHR_MAX_CARDS 6
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@ -124,6 +124,7 @@ struct pcxhr_mgr {
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unsigned char xlx_cfg; /* copy of PCXHR_XLX_CFG register */
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unsigned char xlx_selmic; /* copy of PCXHR_XLX_SELMIC register */
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unsigned char dsp_reset; /* copy of PCXHR_DSP_RESET register */
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};
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@ -53,6 +53,8 @@
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#define PCXHR_DSP_RESET_DSP 0x01
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#define PCXHR_DSP_RESET_MUTE 0x02
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#define PCXHR_DSP_RESET_CODEC 0x08
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#define PCXHR_DSP_RESET_GPO_OFFSET 5
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#define PCXHR_DSP_RESET_GPO_MASK 0x60
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/* values for PCHR_XLX_CFG register */
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#define PCXHR_CFG_SYNCDSP_MASK 0x80
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@ -81,6 +83,8 @@
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/* values for PCHR_XLX_STATUS register - READ */
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#define PCXHR_STAT_SRC_LOCK 0x01
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#define PCXHR_STAT_LEVEL_IN 0x02
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#define PCXHR_STAT_GPI_OFFSET 2
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#define PCXHR_STAT_GPI_MASK 0x0C
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#define PCXHR_STAT_MIC_CAPS 0x10
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/* values for PCHR_XLX_STATUS register - WRITE */
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#define PCXHR_STAT_FREQ_SYNC_MASK 0x01
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@ -291,10 +295,11 @@ int hr222_sub_init(struct pcxhr_mgr *mgr)
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PCXHR_OUTPB(mgr, PCXHR_DSP_RESET,
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PCXHR_DSP_RESET_DSP);
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msleep(5);
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PCXHR_OUTPB(mgr, PCXHR_DSP_RESET,
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PCXHR_DSP_RESET_DSP |
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PCXHR_DSP_RESET_MUTE |
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PCXHR_DSP_RESET_CODEC);
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mgr->dsp_reset = PCXHR_DSP_RESET_DSP |
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PCXHR_DSP_RESET_MUTE |
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PCXHR_DSP_RESET_CODEC;
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PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, mgr->dsp_reset);
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/* hr222_write_gpo(mgr, 0); does the same */
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msleep(5);
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/* config AKM */
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@ -496,6 +501,33 @@ int hr222_get_external_clock(struct pcxhr_mgr *mgr,
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}
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int hr222_read_gpio(struct pcxhr_mgr *mgr, int is_gpi, int *value)
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{
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if (is_gpi) {
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unsigned char reg = PCXHR_INPB(mgr, PCXHR_XLX_STATUS);
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*value = (int)(reg & PCXHR_STAT_GPI_MASK) >>
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PCXHR_STAT_GPI_OFFSET;
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} else {
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*value = (int)(mgr->dsp_reset & PCXHR_DSP_RESET_GPO_MASK) >>
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PCXHR_DSP_RESET_GPO_OFFSET;
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}
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return 0;
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}
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int hr222_write_gpo(struct pcxhr_mgr *mgr, int value)
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{
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unsigned char reg = mgr->dsp_reset & ~PCXHR_DSP_RESET_GPO_MASK;
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reg |= (unsigned char)(value << PCXHR_DSP_RESET_GPO_OFFSET) &
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PCXHR_DSP_RESET_GPO_MASK;
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PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, reg);
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mgr->dsp_reset = reg;
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return 0;
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}
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int hr222_update_analog_audio_level(struct snd_pcxhr *chip,
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int is_capture, int channel)
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{
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@ -32,6 +32,9 @@ int hr222_get_external_clock(struct pcxhr_mgr *mgr,
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enum pcxhr_clock_type clock_type,
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int *sample_rate);
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int hr222_read_gpio(struct pcxhr_mgr *mgr, int is_gpi, int *value);
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int hr222_write_gpo(struct pcxhr_mgr *mgr, int value);
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#define HR222_LINE_PLAYBACK_LEVEL_MIN 0 /* -25.5 dB */
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#define HR222_LINE_PLAYBACK_ZERO_LEVEL 51 /* 0.0 dB */
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#define HR222_LINE_PLAYBACK_LEVEL_MAX 99 /* +24.0 dB */
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@ -789,11 +789,15 @@ static int pcxhr_clock_type_put(struct snd_kcontrol *kcontrol,
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if (mgr->use_clock_type != ucontrol->value.enumerated.item[0]) {
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mutex_lock(&mgr->setup_mutex);
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mgr->use_clock_type = ucontrol->value.enumerated.item[0];
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if (mgr->use_clock_type)
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rate = 0;
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if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
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pcxhr_get_external_clock(mgr, mgr->use_clock_type,
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&rate);
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else
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} else {
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rate = mgr->sample_rate;
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if (!rate)
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rate = 48000;
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}
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if (rate) {
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pcxhr_set_clock(mgr, rate);
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if (mgr->sample_rate)
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