ARM: perf: move CPU-specific PMU handling code into separate file
This patch moves the CPU-specific PMU handling code out of perf_event.c and into perf_event_cpu.c. Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon
parent
6dbc002970
commit
5505b206ca
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@ -69,7 +69,7 @@ obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o
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obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o
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obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o
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obj-$(CONFIG_IWMMXT) += iwmmxt.o
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obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
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obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o
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AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt
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obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o
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@ -12,54 +12,15 @@
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*/
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#define pr_fmt(fmt) "hw perfevents: " fmt
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#include <linux/bitmap.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/of.h>
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#include <linux/perf_event.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/uaccess.h>
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#include <linux/pm_runtime.h>
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#include <linux/uaccess.h>
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#include <asm/cputype.h>
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#include <asm/irq.h>
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#include <asm/irq_regs.h>
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#include <asm/pmu.h>
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#include <asm/stacktrace.h>
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/* Set at runtime when we know what CPU type we are. */
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static struct arm_pmu *cpu_pmu;
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static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
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static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
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static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
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/*
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* Despite the names, these two functions are CPU-specific and are used
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* by the OProfile/perf code.
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*/
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const char *perf_pmu_name(void)
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{
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if (!cpu_pmu)
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return NULL;
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return cpu_pmu->pmu.name;
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}
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EXPORT_SYMBOL_GPL(perf_pmu_name);
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int perf_num_counters(void)
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{
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int max_events = 0;
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if (cpu_pmu != NULL)
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max_events = cpu_pmu->num_events;
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return max_events;
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}
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EXPORT_SYMBOL_GPL(perf_num_counters);
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static int
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armpmu_map_cache_event(const unsigned (*cache_map)
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[PERF_COUNT_HW_CACHE_MAX]
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@ -608,176 +569,6 @@ int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
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return perf_pmu_register(&armpmu->pmu, name, type);
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}
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/* Include the PMU-specific implementations. */
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#include "perf_event_xscale.c"
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#include "perf_event_v6.c"
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#include "perf_event_v7.c"
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static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
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{
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return &__get_cpu_var(cpu_hw_events);
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}
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static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
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{
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int cpu;
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for_each_possible_cpu(cpu) {
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struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
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events->events = per_cpu(hw_events, cpu);
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events->used_mask = per_cpu(used_mask, cpu);
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raw_spin_lock_init(&events->pmu_lock);
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}
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cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
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/* Ensure the PMU has sane values out of reset. */
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if (cpu_pmu && cpu_pmu->reset)
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on_each_cpu(cpu_pmu->reset, NULL, 1);
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}
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/*
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* PMU hardware loses all context when a CPU goes offline.
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* When a CPU is hotplugged back in, since some hardware registers are
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* UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
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* junk values out of them.
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*/
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static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
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unsigned long action, void *hcpu)
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{
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if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
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return NOTIFY_DONE;
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if (cpu_pmu && cpu_pmu->reset)
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cpu_pmu->reset(NULL);
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return NOTIFY_OK;
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}
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static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
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.notifier_call = cpu_pmu_notify,
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};
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/*
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* PMU platform driver and devicetree bindings.
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*/
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static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = {
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{.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init},
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{.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init},
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{.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init},
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{.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init},
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{.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init},
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{.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
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{.compatible = "arm,arm1176-pmu", .data = armv6pmu_init},
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{.compatible = "arm,arm1136-pmu", .data = armv6pmu_init},
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{},
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};
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static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
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{.name = "arm-pmu"},
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{},
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};
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/*
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* CPU PMU identification and probing.
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*/
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static struct arm_pmu *__devinit probe_current_pmu(void)
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{
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struct arm_pmu *pmu = NULL;
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int cpu = get_cpu();
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unsigned long cpuid = read_cpuid_id();
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unsigned long implementor = (cpuid & 0xFF000000) >> 24;
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unsigned long part_number = (cpuid & 0xFFF0);
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pr_info("probing PMU on CPU %d\n", cpu);
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/* ARM Ltd CPUs. */
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if (0x41 == implementor) {
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switch (part_number) {
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case 0xB360: /* ARM1136 */
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case 0xB560: /* ARM1156 */
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case 0xB760: /* ARM1176 */
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pmu = armv6pmu_init();
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break;
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case 0xB020: /* ARM11mpcore */
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pmu = armv6mpcore_pmu_init();
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break;
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case 0xC080: /* Cortex-A8 */
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pmu = armv7_a8_pmu_init();
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break;
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case 0xC090: /* Cortex-A9 */
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pmu = armv7_a9_pmu_init();
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break;
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case 0xC050: /* Cortex-A5 */
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pmu = armv7_a5_pmu_init();
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break;
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case 0xC0F0: /* Cortex-A15 */
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pmu = armv7_a15_pmu_init();
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break;
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case 0xC070: /* Cortex-A7 */
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pmu = armv7_a7_pmu_init();
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break;
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}
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/* Intel CPUs [xscale]. */
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} else if (0x69 == implementor) {
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part_number = (cpuid >> 13) & 0x7;
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switch (part_number) {
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case 1:
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pmu = xscale1pmu_init();
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break;
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case 2:
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pmu = xscale2pmu_init();
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break;
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}
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}
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put_cpu();
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return pmu;
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}
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static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
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{
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const struct of_device_id *of_id;
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struct arm_pmu *(*init_fn)(void);
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struct device_node *node = pdev->dev.of_node;
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if (cpu_pmu) {
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pr_info("attempt to register multiple PMU devices!");
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return -ENOSPC;
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}
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if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
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init_fn = of_id->data;
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cpu_pmu = init_fn();
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} else {
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cpu_pmu = probe_current_pmu();
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}
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if (!cpu_pmu)
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return -ENODEV;
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cpu_pmu->plat_device = pdev;
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cpu_pmu_init(cpu_pmu);
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register_cpu_notifier(&cpu_pmu_hotplug_notifier);
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armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
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return 0;
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}
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static struct platform_driver cpu_pmu_driver = {
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.driver = {
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.name = "arm-pmu",
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.pm = &armpmu_dev_pm_ops,
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.of_match_table = cpu_pmu_of_device_ids,
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},
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.probe = cpu_pmu_device_probe,
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.id_table = cpu_pmu_plat_device_ids,
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};
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static int __init register_pmu_driver(void)
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{
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return platform_driver_register(&cpu_pmu_driver);
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}
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device_initcall(register_pmu_driver);
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/*
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* Callchain handling code.
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*/
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@ -0,0 +1,231 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2012 ARM Limited
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*/
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#define pr_fmt(fmt) "CPU PMU: " fmt
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#include <linux/bitmap.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <asm/cputype.h>
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#include <asm/irq_regs.h>
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#include <asm/pmu.h>
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/* Set at runtime when we know what CPU type we are. */
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static struct arm_pmu *cpu_pmu;
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static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
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static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
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static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
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/*
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* Despite the names, these two functions are CPU-specific and are used
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* by the OProfile/perf code.
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*/
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const char *perf_pmu_name(void)
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{
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if (!cpu_pmu)
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return NULL;
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return cpu_pmu->pmu.name;
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}
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EXPORT_SYMBOL_GPL(perf_pmu_name);
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int perf_num_counters(void)
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{
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int max_events = 0;
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if (cpu_pmu != NULL)
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max_events = cpu_pmu->num_events;
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return max_events;
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}
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EXPORT_SYMBOL_GPL(perf_num_counters);
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/* Include the PMU-specific implementations. */
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#include "perf_event_xscale.c"
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#include "perf_event_v6.c"
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#include "perf_event_v7.c"
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static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
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{
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return &__get_cpu_var(cpu_hw_events);
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}
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static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
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{
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int cpu;
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for_each_possible_cpu(cpu) {
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struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
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events->events = per_cpu(hw_events, cpu);
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events->used_mask = per_cpu(used_mask, cpu);
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raw_spin_lock_init(&events->pmu_lock);
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}
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cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
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/* Ensure the PMU has sane values out of reset. */
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if (cpu_pmu && cpu_pmu->reset)
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on_each_cpu(cpu_pmu->reset, NULL, 1);
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}
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/*
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* PMU hardware loses all context when a CPU goes offline.
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* When a CPU is hotplugged back in, since some hardware registers are
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* UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
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* junk values out of them.
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*/
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static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
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unsigned long action, void *hcpu)
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{
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if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
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return NOTIFY_DONE;
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if (cpu_pmu && cpu_pmu->reset)
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cpu_pmu->reset(NULL);
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return NOTIFY_OK;
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}
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static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
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.notifier_call = cpu_pmu_notify,
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};
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/*
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* PMU platform driver and devicetree bindings.
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*/
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static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = {
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{.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init},
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{.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init},
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{.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init},
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{.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init},
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{.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init},
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{.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
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{.compatible = "arm,arm1176-pmu", .data = armv6pmu_init},
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{.compatible = "arm,arm1136-pmu", .data = armv6pmu_init},
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{},
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};
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static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
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{.name = "arm-pmu"},
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{},
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};
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/*
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* CPU PMU identification and probing.
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*/
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static struct arm_pmu *__devinit probe_current_pmu(void)
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{
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struct arm_pmu *pmu = NULL;
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int cpu = get_cpu();
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unsigned long cpuid = read_cpuid_id();
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unsigned long implementor = (cpuid & 0xFF000000) >> 24;
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unsigned long part_number = (cpuid & 0xFFF0);
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pr_info("probing PMU on CPU %d\n", cpu);
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/* ARM Ltd CPUs. */
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if (0x41 == implementor) {
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switch (part_number) {
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case 0xB360: /* ARM1136 */
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case 0xB560: /* ARM1156 */
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case 0xB760: /* ARM1176 */
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pmu = armv6pmu_init();
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break;
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case 0xB020: /* ARM11mpcore */
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pmu = armv6mpcore_pmu_init();
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break;
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case 0xC080: /* Cortex-A8 */
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pmu = armv7_a8_pmu_init();
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break;
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case 0xC090: /* Cortex-A9 */
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pmu = armv7_a9_pmu_init();
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break;
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case 0xC050: /* Cortex-A5 */
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pmu = armv7_a5_pmu_init();
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break;
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case 0xC0F0: /* Cortex-A15 */
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pmu = armv7_a15_pmu_init();
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break;
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case 0xC070: /* Cortex-A7 */
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pmu = armv7_a7_pmu_init();
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break;
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}
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/* Intel CPUs [xscale]. */
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} else if (0x69 == implementor) {
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part_number = (cpuid >> 13) & 0x7;
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switch (part_number) {
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case 1:
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pmu = xscale1pmu_init();
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break;
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case 2:
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pmu = xscale2pmu_init();
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break;
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}
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}
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put_cpu();
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return pmu;
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}
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static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
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{
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const struct of_device_id *of_id;
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struct arm_pmu *(*init_fn)(void);
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struct device_node *node = pdev->dev.of_node;
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if (cpu_pmu) {
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pr_info("attempt to register multiple PMU devices!");
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return -ENOSPC;
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}
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if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
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init_fn = of_id->data;
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cpu_pmu = init_fn();
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} else {
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cpu_pmu = probe_current_pmu();
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}
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if (!cpu_pmu)
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return -ENODEV;
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||||
|
||||
cpu_pmu->plat_device = pdev;
|
||||
cpu_pmu_init(cpu_pmu);
|
||||
register_cpu_notifier(&cpu_pmu_hotplug_notifier);
|
||||
armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver cpu_pmu_driver = {
|
||||
.driver = {
|
||||
.name = "arm-pmu",
|
||||
.pm = &armpmu_dev_pm_ops,
|
||||
.of_match_table = cpu_pmu_of_device_ids,
|
||||
},
|
||||
.probe = cpu_pmu_device_probe,
|
||||
.id_table = cpu_pmu_plat_device_ids,
|
||||
};
|
||||
|
||||
static int __init register_pmu_driver(void)
|
||||
{
|
||||
return platform_driver_register(&cpu_pmu_driver);
|
||||
}
|
||||
device_initcall(register_pmu_driver);
|
||||
Loading…
Reference in New Issue