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ASoC: fsl_ssi: Fix the incorrect limitation of the bit clock rate 

According to i.MX Reference Manual, the bit-clock frequency generated
by SSI must be never greater than 1/5 of the peripheral clock frequency.

This peripheral clock, however, is not baudclk but the IPG clock (i.e.
ssi_private->clk in the fsl_ssi driver).

So this patch just simply fixes the incorrect limitation applied to
the bit clock (baudclk) rate.

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Nicolin Chen 2015-02-10 21:31:43 -08:00 committed by Mark Brown
parent bfa76d4957
commit 541b03ad6c
1 changed files with 7 additions and 4 deletions
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11
sound/soc/fsl/fsl_ssi.c
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@ -603,10 +603,6 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
factor = (div2 + 1) * (7 * psr + 1) * 2; factor = (div2 + 1) * (7 * psr + 1) * 2;
for (i = 0; i < 255; i++) { for (i = 0; i < 255; i++) {
/* The bclk rate must be smaller than 1/5 sysclk rate */
if (factor * (i + 1) < 5)
continue;
tmprate = freq * factor * (i + 2); tmprate = freq * factor * (i + 2);
if (baudclk_is_used) if (baudclk_is_used)
@ -614,6 +610,13 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
else else
clkrate = clk_round_rate(ssi_private->baudclk, tmprate); clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
/*
* Hardware limitation: The bclk rate must be
* never greater than 1/5 IPG clock rate
*/
if (clkrate * 5 > clk_get_rate(ssi_private->clk))
continue;
clkrate /= factor; clkrate /= factor;
afreq = clkrate / (i + 1); afreq = clkrate / (i + 1);