intel_mid_dma: Add runtime PM support
This patch adds runtime PM support in this dma driver for 4 PCI Controllers Whenever the driver is idle (no channels grabbed), it can go to low power state It also adds the PCI suspend and resume support Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Koul, Vinod
Dan Williams
parent
cc60f8878e
commit
53a61badf4
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@ -25,6 +25,7 @@
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*/
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/pm_runtime.h>
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#include <linux/intel_mid_dma.h>
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#define MAX_CHAN 4 /*max ch across controllers*/
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@ -247,13 +248,13 @@ static void midc_dostart(struct intel_mid_dma_chan *midc,
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struct middma_device *mid = to_middma_device(midc->chan.device);
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/* channel is idle */
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if (midc->in_use && test_ch_en(midc->dma_base, midc->ch_id)) {
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if (midc->busy && test_ch_en(midc->dma_base, midc->ch_id)) {
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/*error*/
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pr_err("ERR_MDMA: channel is busy in start\n");
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/* The tasklet will hopefully advance the queue... */
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return;
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}
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midc->busy = true;
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/*write registers and en*/
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iowrite32(first->sar, midc->ch_regs + SAR);
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iowrite32(first->dar, midc->ch_regs + DAR);
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@ -290,7 +291,7 @@ static void midc_descriptor_complete(struct intel_mid_dma_chan *midc,
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param_txd = txd->callback_param;
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list_move(&desc->desc_node, &midc->free_list);
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midc->busy = false;
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spin_unlock_bh(&midc->lock);
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if (callback_txd) {
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pr_debug("MDMA: TXD callback set ... calling\n");
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@ -434,7 +435,7 @@ static int intel_mid_dma_device_control(struct dma_chan *chan,
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return -ENXIO;
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spin_lock_bh(&midc->lock);
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if (midc->in_use == false) {
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if (midc->busy == false) {
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spin_unlock_bh(&midc->lock);
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return 0;
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}
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@ -618,11 +619,11 @@ static void intel_mid_dma_free_chan_resources(struct dma_chan *chan)
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struct middma_device *mid = to_middma_device(chan->device);
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struct intel_mid_dma_desc *desc, *_desc;
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if (true == midc->in_use) {
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if (true == midc->busy) {
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/*trying to free ch in use!!!!!*/
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pr_err("ERR_MDMA: trying to free ch in use\n");
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}
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pm_runtime_put(&mid->pdev->dev);
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spin_lock_bh(&midc->lock);
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midc->descs_allocated = 0;
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list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) {
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@ -639,6 +640,7 @@ static void intel_mid_dma_free_chan_resources(struct dma_chan *chan)
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}
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spin_unlock_bh(&midc->lock);
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midc->in_use = false;
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midc->busy = false;
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/* Disable CH interrupts */
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iowrite32(MASK_INTR_REG(midc->ch_id), mid->dma_base + MASK_BLOCK);
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iowrite32(MASK_INTR_REG(midc->ch_id), mid->dma_base + MASK_ERR);
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@ -659,11 +661,20 @@ static int intel_mid_dma_alloc_chan_resources(struct dma_chan *chan)
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dma_addr_t phys;
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int i = 0;
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pm_runtime_get_sync(&mid->pdev->dev);
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if (mid->state == SUSPENDED) {
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if (dma_resume(mid->pdev)) {
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pr_err("ERR_MDMA: resume failed");
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return -EFAULT;
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}
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}
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/* ASSERT: channel is idle */
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if (test_ch_en(mid->dma_base, midc->ch_id)) {
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/*ch is not idle*/
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pr_err("ERR_MDMA: ch not idle\n");
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pm_runtime_put(&mid->pdev->dev);
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return -EIO;
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}
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midc->completed = chan->cookie = 1;
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@ -674,6 +685,7 @@ static int intel_mid_dma_alloc_chan_resources(struct dma_chan *chan)
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desc = pci_pool_alloc(mid->dma_pool, GFP_KERNEL, &phys);
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if (!desc) {
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pr_err("ERR_MDMA: desc failed\n");
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pm_runtime_put(&mid->pdev->dev);
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return -ENOMEM;
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/*check*/
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}
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@ -686,7 +698,8 @@ static int intel_mid_dma_alloc_chan_resources(struct dma_chan *chan)
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list_add_tail(&desc->desc_node, &midc->free_list);
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}
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spin_unlock_bh(&midc->lock);
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midc->in_use = false;
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midc->in_use = true;
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midc->busy = false;
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pr_debug("MID_DMA: Desc alloc done ret: %d desc\n", i);
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return i;
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}
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@ -884,6 +897,7 @@ static int mid_setup_dma(struct pci_dev *pdev)
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pr_debug("MDMA:Adding %d channel for this controller\n", dma->max_chan);
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/*init CH structures*/
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dma->intr_mask = 0;
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dma->state = RUNNING;
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for (i = 0; i < dma->max_chan; i++) {
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struct intel_mid_dma_chan *midch = &dma->ch[i];
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@ -1070,6 +1084,9 @@ static int __devinit intel_mid_dma_probe(struct pci_dev *pdev,
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if (err)
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goto err_dma;
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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pm_runtime_allow(&pdev->dev);
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return 0;
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err_dma:
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@ -1104,6 +1121,85 @@ static void __devexit intel_mid_dma_remove(struct pci_dev *pdev)
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pci_disable_device(pdev);
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}
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/* Power Management */
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/*
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* dma_suspend - PCI suspend function
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*
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* @pci: PCI device structure
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* @state: PM message
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*
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* This function is called by OS when a power event occurs
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*/
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int dma_suspend(struct pci_dev *pci, pm_message_t state)
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{
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int i;
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struct middma_device *device = pci_get_drvdata(pci);
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pr_debug("MDMA: dma_suspend called\n");
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for (i = 0; i < device->max_chan; i++) {
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if (device->ch[i].in_use)
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return -EAGAIN;
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}
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device->state = SUSPENDED;
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pci_set_drvdata(pci, device);
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pci_save_state(pci);
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pci_disable_device(pci);
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pci_set_power_state(pci, PCI_D3hot);
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return 0;
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}
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/**
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* dma_resume - PCI resume function
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*
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* @pci: PCI device structure
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*
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* This function is called by OS when a power event occurs
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*/
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int dma_resume(struct pci_dev *pci)
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{
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int ret;
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struct middma_device *device = pci_get_drvdata(pci);
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pr_debug("MDMA: dma_resume called\n");
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pci_set_power_state(pci, PCI_D0);
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pci_restore_state(pci);
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ret = pci_enable_device(pci);
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if (ret) {
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pr_err("MDMA: device cant be enabled for %x\n", pci->device);
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return ret;
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}
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device->state = RUNNING;
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iowrite32(REG_BIT0, device->dma_base + DMA_CFG);
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pci_set_drvdata(pci, device);
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return 0;
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}
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static int dma_runtime_suspend(struct device *dev)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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return dma_suspend(pci_dev, PMSG_SUSPEND);
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}
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static int dma_runtime_resume(struct device *dev)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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return dma_resume(pci_dev);
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}
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static int dma_runtime_idle(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct middma_device *device = pci_get_drvdata(pdev);
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int i;
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for (i = 0; i < device->max_chan; i++) {
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if (device->ch[i].in_use)
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return -EAGAIN;
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}
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return pm_schedule_suspend(dev, 0);
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}
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/******************************************************************************
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* PCI stuff
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*/
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@ -1116,11 +1212,24 @@ static struct pci_device_id intel_mid_dma_ids[] = {
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};
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MODULE_DEVICE_TABLE(pci, intel_mid_dma_ids);
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static const struct dev_pm_ops intel_mid_dma_pm = {
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.runtime_suspend = dma_runtime_suspend,
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.runtime_resume = dma_runtime_resume,
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.runtime_idle = dma_runtime_idle,
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};
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static struct pci_driver intel_mid_dma_pci = {
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.name = "Intel MID DMA",
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.id_table = intel_mid_dma_ids,
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.probe = intel_mid_dma_probe,
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.remove = __devexit_p(intel_mid_dma_remove),
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#ifdef CONFIG_PM
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.suspend = dma_suspend,
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.resume = dma_resume,
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.driver = {
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.pm = &intel_mid_dma_pm,
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},
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#endif
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};
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static int __init intel_mid_dma_init(void)
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@ -29,7 +29,7 @@
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#include <linux/dmapool.h>
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#include <linux/pci_ids.h>
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#define INTEL_MID_DMA_DRIVER_VERSION "1.0.5"
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#define INTEL_MID_DMA_DRIVER_VERSION "1.0.6"
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#define REG_BIT0 0x00000001
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#define REG_BIT8 0x00000100
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@ -152,6 +152,7 @@ union intel_mid_dma_cfg_hi {
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u32 cfg_hi;
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};
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/**
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* struct intel_mid_dma_chan - internal mid representation of a DMA channel
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* @chan: dma_chan strcture represetation for mid chan
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@ -166,6 +167,7 @@ union intel_mid_dma_cfg_hi {
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* @slave: dma slave struture
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* @descs_allocated: total number of decsiptors allocated
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* @dma: dma device struture pointer
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* @busy: bool representing if ch is busy (active txn) or not
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* @in_use: bool representing if ch is in use or not
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*/
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struct intel_mid_dma_chan {
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@ -181,6 +183,7 @@ struct intel_mid_dma_chan {
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struct intel_mid_dma_slave *slave;
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unsigned int descs_allocated;
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struct middma_device *dma;
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bool busy;
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bool in_use;
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};
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@ -190,6 +193,10 @@ static inline struct intel_mid_dma_chan *to_intel_mid_dma_chan(
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return container_of(chan, struct intel_mid_dma_chan, chan);
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}
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enum intel_mid_dma_state {
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RUNNING = 0,
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SUSPENDED,
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};
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/**
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* struct middma_device - internal representation of a DMA device
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* @pdev: PCI device
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@ -205,6 +212,7 @@ static inline struct intel_mid_dma_chan *to_intel_mid_dma_chan(
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* @max_chan: max number of chs supported (from drv_data)
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* @block_size: Block size of DMA transfer supported (from drv_data)
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* @pimr_mask: MMIO register addr for periphral interrupt (from drv_data)
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* @state: dma PM device state
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*/
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struct middma_device {
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struct pci_dev *pdev;
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@ -220,6 +228,7 @@ struct middma_device {
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int max_chan;
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int block_size;
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unsigned int pimr_mask;
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enum intel_mid_dma_state state;
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};
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static inline struct middma_device *to_middma_device(struct dma_device *common)
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@ -257,4 +266,7 @@ static inline struct intel_mid_dma_desc *to_intel_mid_dma_desc
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{
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return container_of(txd, struct intel_mid_dma_desc, txd);
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}
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int dma_resume(struct pci_dev *pci);
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#endif /*__INTEL_MID_DMAC_REGS_H__*/
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