arm64: dts: lx2160a: add tmu device node
Add the TMU (Thermal Monitoring Unit) device node to enable TMU feature. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Yuantian Tang
Shawn Guo
parent
95993238b2
commit
5363eaaeb8
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@ -6,6 +6,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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/memreserve/ 0x80000000 0x00010000;
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@ -20,7 +21,7 @@
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#size-cells = <0>;
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// 8 clusters having 2 Cortex-A72 cores each
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cpu@0 {
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -34,9 +35,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster0_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@1 {
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -50,9 +52,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster0_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@100 {
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cpu100: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -66,9 +69,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster1_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@101 {
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cpu101: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -82,9 +86,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster1_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@200 {
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cpu200: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -98,9 +103,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster2_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@201 {
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cpu201: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -114,9 +120,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster2_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@300 {
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cpu300: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -130,9 +137,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster3_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@301 {
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cpu301: cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -146,9 +154,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster3_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@400 {
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cpu400: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -162,9 +171,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster4_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@401 {
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cpu401: cpu@401 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -178,9 +188,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster4_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@500 {
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cpu500: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -194,9 +205,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster5_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@501 {
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cpu501: cpu@501 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -210,9 +222,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster5_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@600 {
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cpu600: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -226,9 +239,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster6_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@601 {
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cpu601: cpu@601 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -242,9 +256,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster6_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@700 {
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cpu700: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -258,9 +273,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster7_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cpu@701 {
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cpu701: cpu@701 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@ -274,6 +290,7 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster7_l2>;
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cpu-idle-states = <&cpu_pw15>;
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#cooling-cells = <2>;
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};
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cluster0_l2: l2-cache0 {
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@ -418,6 +435,51 @@
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clock-output-names = "sysclk";
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};
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thermal-zones {
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core_thermal1: core-thermal1 {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 0>;
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trips {
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core_cluster_alert: core-cluster-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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core_cluster_crit: core-cluster-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&core_cluster_alert>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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@ -478,6 +540,20 @@
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little-endian;
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};
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tmu: tmu@1f80000 {
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compatible = "fsl,qoriq-tmu";
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reg = <0x0 0x1f80000 0x0 0x10000>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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fsl,tmu-range = <0x800000e6 0x8001017d>;
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fsl,tmu-calibration =
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/* Calibration data group 1 */
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<0x00000000 0x00000035
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/* Calibration data group 2 */
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0x00010001 0x00000154>;
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little-endian;
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#thermal-sensor-cells = <1>;
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};
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i2c0: i2c@2000000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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