[ARM] 4521/2: S3C: Reorganise VA mapping headers
Reorganise the definition of the virtual addresses used into a common header and update the users to rename S3C2410 items into a more common S3C defined macros. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Ben Dooks
Russell King
parent
bf2a3a26d1
commit
530ef3c2a9
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@ -13,32 +13,19 @@
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#ifndef __ASM_ARCH_MAP_H
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#define __ASM_ARCH_MAP_H
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/* we have a bit of a tight squeeze to fit all our registers from
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* 0xF00000000 upwards, since we use all of the nGCS space in some
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* capacity, and also need to fit the S3C2410 registers in as well...
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*
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* we try to ensure stuff like the IRQ registers are available for
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* an single MOVS instruction (ie, only 8 bits of set data)
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*
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* Note, we are trying to remove some of these from the implementation
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* as they are only useful to certain drivers...
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*/
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#include <asm/plat-s3c/map.h>
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#ifndef __ASSEMBLY__
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#define S3C2410_ADDR(x) ((void __iomem __force *)0xF0000000 + (x))
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#else
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#define S3C2410_ADDR(x) (0xF0000000 + (x))
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#endif
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#define S3C2410_ADDR(x) S3C_ADDR(x)
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/* interrupt controller is the first thing we put in, to make
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* the assembly code for the irq detection easier
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*/
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#define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000)
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#define S3C24XX_VA_IRQ S3C_VA_IRQ
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#define S3C2410_PA_IRQ (0x4A000000)
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#define S3C24XX_SZ_IRQ SZ_1M
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/* memory controller registers */
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#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
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#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
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#define S3C2410_PA_MEMCTRL (0x48000000)
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#define S3C24XX_SZ_MEMCTRL SZ_1M
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@ -51,7 +38,7 @@
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#define S3C24XX_SZ_DMA SZ_1M
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/* Clock and Power management */
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#define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00200000)
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#define S3C24XX_VA_CLKPWR S3C_VA_SYS
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#define S3C2410_PA_CLKPWR (0x4C000000)
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#define S3C24XX_SZ_CLKPWR SZ_1M
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@ -64,12 +51,12 @@
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#define S3C24XX_SZ_NAND SZ_1M
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/* UARTs */
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#define S3C24XX_VA_UART S3C2410_ADDR(0x00400000)
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#define S3C24XX_VA_UART S3C_VA_UART
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#define S3C2410_PA_UART (0x50000000)
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#define S3C24XX_SZ_UART SZ_1M
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/* Timers */
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#define S3C24XX_VA_TIMER S3C2410_ADDR(0x00500000)
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#define S3C24XX_VA_TIMER S3C_VA_TIMER
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#define S3C2410_PA_TIMER (0x51000000)
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#define S3C24XX_SZ_TIMER SZ_1M
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@ -78,7 +65,7 @@
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#define S3C24XX_SZ_USBDEV SZ_1M
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/* Watchdog */
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#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000)
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#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
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#define S3C2410_PA_WATCHDOG (0x53000000)
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#define S3C24XX_SZ_WATCHDOG SZ_1M
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@ -96,7 +83,7 @@
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* it is the same distance apart from the UART in the
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* phsyical address space, as the initial mapping for the IO
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* is done as a 1:1 maping. This puts it (currently) at
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* 0xF6800000, which is not in the way of any current mapping
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* 0xFA800000, which is not in the way of any current mapping
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* by the base system.
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*/
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@ -153,7 +140,6 @@
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#define S3C2410_SDRAM_PA (S3C2410_CS6)
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/* Use a single interface for common resources between S3C24XX cpus */
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#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
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@ -0,0 +1,40 @@
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/* linux/include/asm-arm/plat-s3c/map.h
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*
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* Copyright 2003, 2007 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C - Memory map definitions (virtual addresses)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PLAT_MAP_H
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#define __ASM_PLAT_MAP_H __FILE__
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/* Fit all our registers in at 0xF4000000 upwards, trying to use as
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* little of the VA space as possible so vmalloc and friends have a
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* better chance of getting memory.
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*
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* we try to ensure stuff like the IRQ registers are available for
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* an single MOVS instruction (ie, only 8 bits of set data)
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*/
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#define S3C_ADDR_BASE (0xF4000000)
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#ifndef __ASSEMBLY__
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#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x))
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#else
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#define S3C_ADDR(x) (S3C_ADDR_BASE + (x))
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#endif
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#define S3C_VA_IRQ S3C_ADDR(0x000000000) /* irq controller(s) */
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#define S3C_VA_SYS S3C_ADDR(0x001000000) /* system control */
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#define S3C_VA_MEM S3C_ADDR(0x002000000) /* system control */
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#define S3C_VA_TIMER S3C_ADDR(0x003000000) /* timer block */
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#define S3C_VA_WATCHDOG S3C_ADDR(0x004000000) /* watchdog */
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#define S3C_VA_UART S3C_ADDR(0x010000000) /* UART */
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#endif /* __ASM_PLAT_MAP_H */
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@ -32,10 +32,10 @@
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#ifndef __ASM_ARM_REGS_SERIAL_H
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#define __ASM_ARM_REGS_SERIAL_H
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#define S3C24XX_VA_UART0 (S3C24XX_VA_UART)
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#define S3C24XX_VA_UART1 (S3C24XX_VA_UART + 0x4000 )
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#define S3C24XX_VA_UART2 (S3C24XX_VA_UART + 0x8000 )
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#define S3C24XX_VA_UART3 (S3C24XX_VA_UART + 0xC000 )
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#define S3C24XX_VA_UART0 (S3C_VA_UART)
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#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
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#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
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#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
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#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
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#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
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@ -14,12 +14,12 @@
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#ifndef __ASM_ARCH_REGS_TIMER_H
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#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
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#define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x))
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#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c))
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#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
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#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
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#define S3C2410_TCFG0 S3C2410_TIMERREG(0x00)
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#define S3C2410_TCFG1 S3C2410_TIMERREG(0x04)
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#define S3C2410_TCON S3C2410_TIMERREG(0x08)
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#define S3C2410_TCFG0 S3C_TIMERREG(0x00)
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#define S3C2410_TCFG1 S3C_TIMERREG(0x04)
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#define S3C2410_TCON S3C_TIMERREG(0x08)
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#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
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#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
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@ -71,9 +71,9 @@
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/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
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#define S3C2410_TCNTB(tmr) S3C2410_TIMERREG2(tmr, 0x00)
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#define S3C2410_TCMPB(tmr) S3C2410_TIMERREG2(tmr, 0x04)
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#define S3C2410_TCNTO(tmr) S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
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#define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00)
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#define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04)
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#define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
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#define S3C2410_TCON_T4RELOAD (1<<22)
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#define S3C2410_TCON_T4MANUALUPD (1<<21)
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@ -14,11 +14,11 @@
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#ifndef __ASM_ARCH_REGS_WATCHDOG_H
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#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
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#define S3C2410_WDOGREG(x) ((x) + S3C24XX_VA_WATCHDOG)
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#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
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#define S3C2410_WTCON S3C2410_WDOGREG(0x00)
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#define S3C2410_WTDAT S3C2410_WDOGREG(0x04)
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#define S3C2410_WTCNT S3C2410_WDOGREG(0x08)
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#define S3C2410_WTCON S3C_WDOGREG(0x00)
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#define S3C2410_WTDAT S3C_WDOGREG(0x04)
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#define S3C2410_WTCNT S3C_WDOGREG(0x08)
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/* the watchdog can either generate a reset pulse, or an
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* interrupt.
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