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[ARM] 4461/1: MXC platform and i.MX31ADS core support 

This patch adds the foundation pieces for
the Freescale MXC platforms, including
i.MX2 and i.MX3 based systems.

The bare-bones MX31 support in this patch
boots to the rootdev panic with 8250 serial
console configured "console=ttyS0,115200".
It assumes that Redboot is the boot loader.

Signed-off-by: Quinn Jensen <quinn.jensen@freescale.com>
Acked-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Quinn Jensen 2007-07-09 22:06:53 +01:00 committed by Russell King
parent 4b300c362d
commit 52c543f90c
26 changed files with 1563 additions and 2 deletions
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8
arch/arm/Kconfig
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@ -324,6 +324,12 @@ config ARCH_NS9XXX
<http://www.digi.com/products/microprocessors/index.jsp>
config ARCH_MXC
bool "Freescale MXC/iMX-based"
select ARCH_MTD_XIP
help
Support for Freescale MXC/iMX-based family of processors
config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile"
help
@ -456,6 +462,8 @@ source "arch/arm/mach-realview/Kconfig"
source "arch/arm/mach-at91/Kconfig"
source "arch/arm/plat-mxc/Kconfig"
source "arch/arm/mach-netx/Kconfig"
source "arch/arm/mach-ns9xxx/Kconfig"

3
arch/arm/Makefile
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@ -137,6 +137,8 @@ endif
textofs-$(CONFIG_ARCH_NS9XXX) := 0x00108000
machine-$(CONFIG_ARCH_DAVINCI) := davinci
machine-$(CONFIG_ARCH_KS8695) := ks8695
incdir-$(CONFIG_ARCH_MXC) := mxc
machine-$(CONFIG_ARCH_MX3) := mx3
ifeq ($(CONFIG_ARCH_EBSA110),y)
# This is what happens if you forget the IOCS16 line.
@ -183,6 +185,7 @@ core-$(CONFIG_VFP) += arch/arm/vfp/
core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/
core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/
core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/
core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/
drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
drivers-$(CONFIG_ARCH_CLPS7500) += drivers/acorn/char/

12
arch/arm/mach-mx3/Kconfig Normal file
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@ -0,0 +1,12 @@
menu "MX3 Options"
depends on ARCH_MX3
config MACH_MX31ADS
bool "Support MX31ADS platforms"
default y
help
Include support for MX31ADS platform. This includes specific
configurations for the board and its peripherals.
endmenu

8
arch/arm/mach-mx3/Makefile Normal file
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@ -0,0 +1,8 @@
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y := mm.o time.o
obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o

3
arch/arm/mach-mx3/Makefile.boot Normal file
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@ -0,0 +1,3 @@
zreladdr-y := 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x80800000

64
arch/arm/mach-mx3/mm.c Normal file
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@ -0,0 +1,64 @@
/*
* Copyright (C) 1999,2000 Arm Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* - add MX31 specific definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <asm/hardware.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <asm/arch/common.h>
/*!
* @file mm.c
*
* @brief This file creates static virtual to physical mappings, common to all MX3 boards.
*
* @ingroup Memory
*/
/*!
* This table defines static virtual address mappings for I/O regions.
* These are the mappings common across all MX3 boards.
*/
static struct map_desc mxc_io_desc[] __initdata = {
{
.virtual = X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
.length = X_MEMC_SIZE,
.type = MT_DEVICE
}, {
.virtual = AVIC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AVIC_BASE_ADDR),
.length = AVIC_SIZE,
.type = MT_NONSHARED_DEVICE
},
};
/*!
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mxc_map_io(void)
{
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
}

142
arch/arm/mach-mx3/mx31ads.c Normal file
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@ -0,0 +1,142 @@
/*
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/serial_8250.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include <asm/arch/common.h>
/*!
* @file mx31ads.c
*
* @brief This file contains the board-specific initialization routines.
*
* @ingroup System
*/
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
/*!
* The serial port definition structure.
*/
static struct plat_serial8250_port serial_platform_data[] = {
{
.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
.mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA),
.irq = EXPIO_INT_XUART_INTA,
.uartclk = 14745600,
.regshift = 0,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
}, {
.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
.mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB),
.irq = EXPIO_INT_XUART_INTB,
.uartclk = 14745600,
.regshift = 0,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
},
{},
};
static struct platform_device serial_device = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = serial_platform_data,
},
};
static int __init mxc_init_extuart(void)
{
return platform_device_register(&serial_device);
}
#else
static inline int mxc_init_extuart(void)
{
return 0;
}
#endif
/*!
* This structure defines static mappings for the i.MX31ADS board.
*/
static struct map_desc mx31ads_io_desc[] __initdata = {
{
.virtual = AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
.length = AIPS1_SIZE,
.type = MT_NONSHARED_DEVICE
}, {
.virtual = SPBA0_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
.length = SPBA0_SIZE,
.type = MT_NONSHARED_DEVICE
}, {
.virtual = AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
.length = AIPS2_SIZE,
.type = MT_NONSHARED_DEVICE
}, {
.virtual = CS4_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(CS4_BASE_ADDR),
.length = CS4_SIZE / 2,
.type = MT_DEVICE
},
};
/*!
* Set up static virtual mappings.
*/
void __init mx31ads_map_io(void)
{
mxc_map_io();
iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
}
/*!
* Board specific initialization.
*/
static void __init mxc_board_init(void)
{
mxc_init_extuart();
}
/*
* The following uses standard kernel macros defined in arch.h in order to
* initialize __mach_desc_MX31ADS data structure.
*/
MACHINE_START(MX31ADS, "Freescale MX31ADS")
/* Maintainer: Freescale Semiconductor, Inc. */
.phys_io = AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31ads_map_io,
.init_irq = mxc_init_irq,
.init_machine = mxc_board_init,
.timer = &mxc_timer,
MACHINE_END

152
arch/arm/mach-mx3/time.c Normal file
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@ -0,0 +1,152 @@
/*
* System Timer Interrupt reconfigured to run in free-run mode.
* Author: Vitaly Wool
* Copyright 2004 MontaVista Software Inc.
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*!
* @file time.c
* @brief This file contains OS tick and wdog timer implementations.
*
* This file contains OS tick and wdog timer implementations.
*
* @ingroup Timers
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/hardware.h>
#include <asm/mach/time.h>
#include <asm/io.h>
#include <asm/arch/common.h>
/*!
* This is the timer interrupt service routine to do required tasks.
* It also services the WDOG timer at the frequency of twice per WDOG
* timeout value. For example, if the WDOG's timeout value is 4 (2
* seconds since the WDOG runs at 0.5Hz), it will be serviced once
* every 2/2=1 second.
*
* @param irq GPT interrupt source number (not used)
* @param dev_id this parameter is not used
* @return always returns \b IRQ_HANDLED as defined in
* include/linux/interrupt.h.
*/
static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
{
unsigned int next_match;
write_seqlock(&xtime_lock);
if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF1) {
do {
timer_tick();
next_match = __raw_readl(MXC_GPT_GPTOCR1) + LATCH;
__raw_writel(GPTSR_OF1, MXC_GPT_GPTSR);
__raw_writel(next_match, MXC_GPT_GPTOCR1);
} while ((signed long)(next_match -
__raw_readl(MXC_GPT_GPTCNT)) <= 0);
}
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
}
/*!
* This function is used to obtain the number of microseconds since the last
* timer interrupt. Note that interrupts is disabled by do_gettimeofday().
*
* @return the number of microseconds since the last timer interrupt.
*/
static unsigned long mxc_gettimeoffset(void)
{
unsigned long ticks_to_match, elapsed, usec, tick_usec, i;
/* Get ticks before next timer match */
ticks_to_match =
__raw_readl(MXC_GPT_GPTOCR1) - __raw_readl(MXC_GPT_GPTCNT);
/* We need elapsed ticks since last match */
elapsed = LATCH - ticks_to_match;
/* Now convert them to usec */
/* Insure no overflow when calculating the usec below */
for (i = 1, tick_usec = tick_nsec / 1000;; i *= 2) {
tick_usec /= i;
if ((0xFFFFFFFF / tick_usec) > elapsed)
break;
}
usec = (unsigned long)(elapsed * tick_usec) / (LATCH / i);
return usec;
}
/*!
* The OS tick timer interrupt structure.
*/
static struct irqaction timer_irq = {
.name = "MXC Timer Tick",
.flags = IRQF_DISABLED | IRQF_TIMER,
.handler = mxc_timer_interrupt
};
/*!
* This function is used to initialize the GPT to produce an interrupt
* based on HZ. It is called by start_kernel() during system startup.
*/
void __init mxc_init_time(void)
{
u32 reg, v;
reg = __raw_readl(MXC_GPT_GPTCR);
reg &= ~GPTCR_ENABLE;
__raw_writel(reg, MXC_GPT_GPTCR);
reg |= GPTCR_SWR;
__raw_writel(reg, MXC_GPT_GPTCR);
while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0)
cpu_relax();
reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ;
__raw_writel(reg, MXC_GPT_GPTCR);
/* TODO: get timer rate from clk driver */
v = 66500000;
__raw_writel((v / CLOCK_TICK_RATE) - 1, MXC_GPT_GPTPR);
if ((v % CLOCK_TICK_RATE) != 0) {
pr_info("\nWARNING: Can't generate CLOCK_TICK_RATE at %d Hz\n",
CLOCK_TICK_RATE);
}
pr_info("Actual CLOCK_TICK_RATE is %d Hz\n",
v / ((__raw_readl(MXC_GPT_GPTPR) & 0xFFF) + 1));
reg = __raw_readl(MXC_GPT_GPTCNT);
reg += LATCH;
__raw_writel(reg, MXC_GPT_GPTOCR1);
setup_irq(MXC_INT_GPT, &timer_irq);
reg = __raw_readl(MXC_GPT_GPTCR);
reg =
GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_STOPEN | GPTCR_DOZEN |
GPTCR_WAITEN | GPTCR_ENMOD | GPTCR_ENABLE;
__raw_writel(reg, MXC_GPT_GPTCR);
__raw_writel(GPTIR_OF1IE, MXC_GPT_GPTIR);
}
struct sys_timer mxc_timer = {
.init = mxc_init_time,
.offset = mxc_gettimeoffset,
};

5
arch/arm/mm/Kconfig
View File

@ -345,7 +345,8 @@ config CPU_XSC3
# ARMv6
config CPU_V6
bool "Support ARM V6 processor"
depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3
default y if ARCH_MX3
select CPU_32v6
select CPU_ABRT_EV6
select CPU_CACHE_V6
@ -359,7 +360,7 @@ config CPU_V6
config CPU_32v6K
bool "Support ARM V6K processor extensions" if !SMP
depends on CPU_V6
default y if SMP
default y if SMP && !ARCH_MX3
help
Say Y here if your ARMv6 processor supports the 'K' extension.
This enables the kernel to use some instructions not present

20
arch/arm/plat-mxc/Kconfig Normal file
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@ -0,0 +1,20 @@
if ARCH_MXC
menu "Freescale MXC Implementations"
choice
prompt "MXC/iMX System Type"
default 0
config ARCH_MX3
bool "MX3-based"
help
This enables support for systems based on the Freescale i.MX3 family
endchoice
source "arch/arm/mach-mx3/Kconfig"
endmenu
endif

10
arch/arm/plat-mxc/Makefile Normal file
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@ -0,0 +1,10 @@
#
# Makefile for the linux kernel.
#
# Common support
obj-y := irq.o
obj-m :=
obj-n :=
obj- :=

83
arch/arm/plat-mxc/irq.c Normal file
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@ -0,0 +1,83 @@
/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/arch/common.h>
/*!
* Disable interrupt number "irq" in the AVIC
*
* @param irq interrupt source number
*/
static void mxc_mask_irq(unsigned int irq)
{
__raw_writel(irq, AVIC_INTDISNUM);
}
/*!
* Enable interrupt number "irq" in the AVIC
*
* @param irq interrupt source number
*/
static void mxc_unmask_irq(unsigned int irq)
{
__raw_writel(irq, AVIC_INTENNUM);
}
static struct irq_chip mxc_avic_chip = {
.mask_ack = mxc_mask_irq,
.mask = mxc_mask_irq,
.unmask = mxc_unmask_irq,
};
/*!
* This function initializes the AVIC hardware and disables all the
* interrupts. It registers the interrupt enable and disable functions
* to the kernel for each interrupt source.
*/
void __init mxc_init_irq(void)
{
int i;
u32 reg;
/* put the AVIC into the reset value with
* all interrupts disabled
*/
__raw_writel(0, AVIC_INTCNTL);
__raw_writel(0x1f, AVIC_NIMASK);
/* disable all interrupts */
__raw_writel(0, AVIC_INTENABLEH);
__raw_writel(0, AVIC_INTENABLEL);
/* all IRQ no FIQ */
__raw_writel(0, AVIC_INTTYPEH);
__raw_writel(0, AVIC_INTTYPEL);
for (i = 0; i < MXC_MAX_INT_LINES; i++) {
set_irq_chip(i, &mxc_avic_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
/* Set WDOG2's interrupt the highest priority level (bit 28-31) */
reg = __raw_readl(AVIC_NIPRIORITY6);
reg |= (0xF << 28);
__raw_writel(reg, AVIC_NIPRIORITY6);
printk(KERN_INFO "MXC IRQ initialized\n");
}

142
include/asm-arm/arch-mxc/board-mx31ads.h Normal file
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@ -0,0 +1,142 @@
/*
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
/*!
* @name PBC Controller parameters
*/
/*! @{ */
/*!
* Base address of PBC controller
*/
#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR)
/* Offsets for the PBC Controller register */
/*!
* PBC Board status register offset
*/
#define PBC_BSTAT 0x000002
/*!
* PBC Board control register 1 set address.
*/
#define PBC_BCTRL1_SET 0x000004
/*!
* PBC Board control register 1 clear address.
*/
#define PBC_BCTRL1_CLEAR 0x000006
/*!
* PBC Board control register 2 set address.
*/
#define PBC_BCTRL2_SET 0x000008
/*!
* PBC Board control register 2 clear address.
*/
#define PBC_BCTRL2_CLEAR 0x00000A
/*!
* PBC Board control register 3 set address.
*/
#define PBC_BCTRL3_SET 0x00000C
/*!
* PBC Board control register 3 clear address.
*/
#define PBC_BCTRL3_CLEAR 0x00000E
/*!
* PBC Board control register 4 set address.
*/
#define PBC_BCTRL4_SET 0x000010
/*!
* PBC Board control register 4 clear address.
*/
#define PBC_BCTRL4_CLEAR 0x000012
/*!
* PBC Board status register 1.
*/
#define PBC_BSTAT1 0x000014
/*!
* PBC Board interrupt status register.
*/
#define PBC_INTSTATUS 0x000016
/*!
* PBC Board interrupt current status register.
*/
#define PBC_INTCURR_STATUS 0x000018
/*!
* PBC Interrupt mask register set address.
*/
#define PBC_INTMASK_SET 0x00001A
/*!
* PBC Interrupt mask register clear address.
*/
#define PBC_INTMASK_CLEAR 0x00001C
/*!
* External UART A.
*/
#define PBC_SC16C652_UARTA 0x010000
/*!
* External UART B.
*/
#define PBC_SC16C652_UARTB 0x010010
/*!
* Ethernet Controller IO base address.
*/
#define PBC_CS8900A_IOBASE 0x020000
/*!
* Ethernet Controller Memory base address.
*/
#define PBC_CS8900A_MEMBASE 0x021000
/*!
* Ethernet Controller DMA base address.
*/
#define PBC_CS8900A_DMABASE 0x022000
/*!
* External chip select 0.
*/
#define PBC_XCS0 0x040000
/*!
* LCD Display enable.
*/
#define PBC_LCD_EN_B 0x060000
/*!
* Code test debug enable.
*/
#define PBC_CODE_B 0x070000
/*!
* PSRAM memory select.
*/
#define PBC_PSRAM_B 0x5000000
#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)
#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1)
#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7)
#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12)
#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13)
#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14)
#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15)
#define MXC_MAX_EXP_IO_LINES 16
#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */

20
include/asm-arm/arch-mxc/common.h Normal file
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@ -0,0 +1,20 @@
/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MXC_COMMON_H__
#define __ASM_ARCH_MXC_COMMON_H__
struct sys_timer;
extern void mxc_map_io(void);
extern void mxc_init_irq(void);
extern struct sys_timer mxc_timer;
#endif

21
include/asm-arm/arch-mxc/dma.h Normal file
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@ -0,0 +1,21 @@
/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MXC_DMA_H__
#define __ASM_ARCH_MXC_DMA_H__
/*!
* @file dma.h
* @brief This file contains Unified DMA API for all MXC platforms.
* The API is platform independent.
*
* @ingroup SDMA
*/
#endif

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/*
* Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
@ this macro disables fast irq (not implemented)
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
@ this macro checks which interrupt occured
@ and returns its number in irqnr
@ and returns if an interrupt occured in irqstat
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
@ Load offset & priority of the highest priority
@ interrupt pending from AVIC_NIVECSR
ldr \irqstat, [\base, #0x40]
@ Shift to get the decoded IRQ number, using ASR so
@ 'no interrupt pending' becomes 0xffffffff
mov \irqnr, \irqstat, asr #16
@ set zero flag if IRQ + 1 == 0
adds \tmp, \irqnr, #1
.endm
@ irq priority table (not used)
.macro irq_prio_table
.endm

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/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*!
* @file hardware.h
* @brief This file contains the hardware definitions of the board.
*
* @ingroup System
*/
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#define __ASM_ARCH_MXC_HARDWARE_H__
#include <asm/sizes.h>
#include <asm/arch/mx31.h>
#include <asm/arch/mxc.h>
#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
/*
* ---------------------------------------------------------------------------
* Board specific defines
* ---------------------------------------------------------------------------
*/
#define MXC_EXP_IO_BASE (MXC_GPIO_INT_BASE + MXC_MAX_GPIO_LINES)
#include <asm/arch/board-mx31ads.h>
#ifndef MXC_MAX_EXP_IO_LINES
#define MXC_MAX_EXP_IO_LINES 0
#endif
#define MXC_MAX_VIRTUAL_INTS 16
#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
#define MXC_MAX_INTS (MXC_MAX_INT_LINES + \
MXC_MAX_GPIO_LINES + \
MXC_MAX_EXP_IO_LINES + \
MXC_MAX_VIRTUAL_INTS)
#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */

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/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*!
* @file io.h
* @brief This file contains some memory mapping macros.
* @note There is no real ISA or PCI buses. But have to define these macros
* for some drivers to compile.
*
* @ingroup System
*/
#ifndef __ASM_ARCH_MXC_IO_H__
#define __ASM_ARCH_MXC_IO_H__
/*! Allow IO space to be anywhere in the memory */
#define IO_SPACE_LIMIT 0xffffffff
/*!
* io address mapping macro
*/
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#endif

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/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MXC_IRQS_H__
#define __ASM_ARCH_MXC_IRQS_H__
#include <asm/hardware.h>
/*!
* @file irqs.h
* @brief This file defines the number of normal interrupts and fast interrupts
*
* @ingroup Interrupt
*/
#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE)
#define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x)
/*!
* Number of normal interrupts
*/
#define NR_IRQS MXC_MAX_INTS
/*!
* Number of fast interrupts
*/
#define NR_FIQS MXC_MAX_INTS
#endif /* __ASM_ARCH_MXC_IRQS_H__ */

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/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MXC_MEMORY_H__
#define __ASM_ARCH_MXC_MEMORY_H__
#include <asm/hardware.h>
/*!
* @file memory.h
* @brief This file contains macros needed by the Linux kernel and drivers.
*
* @ingroup Memory
*/
/*!
* Virtual view <-> DMA view memory address translations
* This macro is used to translate the virtual address to an address
* suitable to be passed to set_dma_addr()
*/
#define __virt_to_bus(a) __virt_to_phys(a)
/*!
* Used to convert an address for DMA operations to an address that the
* kernel can use.
*/
#define __bus_to_virt(a) __phys_to_virt(a)
#endif /* __ASM_ARCH_MXC_MEMORY_H__ */

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/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MXC_MX31_H__
#define __ASM_ARCH_MXC_MX31_H__
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif
/*!
* defines the hardware clock tick rate
*/
#define CLOCK_TICK_RATE 16625000
/*
* MX31 memory map:
*
* Virt Phys Size What
* ---------------------------------------------------------------------------
* F8000000 1FFC0000 16K IRAM
* F9000000 30000000 256M L2CC
* FC000000 43F00000 1M AIPS 1
* FC100000 50000000 1M SPBA
* FC200000 53F00000 1M AIPS 2
* FC500000 60000000 128M ROMPATCH
* FC400000 68000000 128M AVIC
* 70000000 256M IPU (MAX M2)
* 80000000 256M CSD0 SDRAM/DDR
* 90000000 256M CSD1 SDRAM/DDR
* A0000000 128M CS0 Flash
* A8000000 128M CS1 Flash
* B0000000 32M CS2
* B2000000 32M CS3
* F4000000 B4000000 32M CS4
* B6000000 32M CS5
* FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
* C0000000 64M PCMCIA/CF
*/
#define CS0_BASE_ADDR 0xA0000000
#define CS1_BASE_ADDR 0xA8000000
#define CS2_BASE_ADDR 0xB0000000
#define CS3_BASE_ADDR 0xB2000000
#define CS4_BASE_ADDR 0xB4000000
#define CS4_BASE_ADDR_VIRT 0xF4000000
#define CS4_SIZE SZ_32M
#define CS5_BASE_ADDR 0xB6000000
#define PCMCIA_MEM_BASE_ADDR 0xBC000000
/*
* IRAM
*/
#define IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
#define IRAM_BASE_ADDR_VIRT 0xF8000000
#define IRAM_SIZE SZ_16K
/*
* L2CC
*/
#define L2CC_BASE_ADDR 0x30000000
#define L2CC_BASE_ADDR_VIRT 0xF9000000
#define L2CC_SIZE SZ_1M
/*
* AIPS 1
*/
#define AIPS1_BASE_ADDR 0x43F00000
#define AIPS1_BASE_ADDR_VIRT 0xFC000000
#define AIPS1_SIZE SZ_1M
#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
/*
* SPBA global module enabled #0
*/
#define SPBA0_BASE_ADDR 0x50000000
#define SPBA0_BASE_ADDR_VIRT 0xFC100000
#define SPBA0_SIZE SZ_1M
#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000)
#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
#define MSHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
/*
* AIPS 2
*/
#define AIPS2_BASE_ADDR 0x53F00000
#define AIPS2_BASE_ADDR_VIRT 0xFC200000
#define AIPS2_SIZE SZ_1M
#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000)
#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000)
#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
/*
* ROMP and AVIC
*/
#define ROMP_BASE_ADDR 0x60000000
#define ROMP_BASE_ADDR_VIRT 0xFC500000
#define ROMP_SIZE SZ_1M
#define AVIC_BASE_ADDR 0x68000000
#define AVIC_BASE_ADDR_VIRT 0xFC400000
#define AVIC_SIZE SZ_1M
/*
* NAND, SDRAM, WEIM, M3IF, EMI controllers
*/
#define X_MEMC_BASE_ADDR 0xB8000000
#define X_MEMC_BASE_ADDR_VIRT 0xFC320000
#define X_MEMC_SIZE SZ_64K
#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
/*
* Memory regions and CS
*/
#define IPU_MEM_BASE_ADDR 0x70000000
#define CSD0_BASE_ADDR 0x80000000
#define CSD1_BASE_ADDR 0x90000000
#define CS0_BASE_ADDR 0xA0000000
#define CS1_BASE_ADDR 0xA8000000
#define CS2_BASE_ADDR 0xB0000000
#define CS3_BASE_ADDR 0xB2000000
#define CS4_BASE_ADDR 0xB4000000
#define CS4_BASE_ADDR_VIRT 0xF4000000
#define CS4_SIZE SZ_32M
#define CS5_BASE_ADDR 0xB6000000
#define PCMCIA_MEM_BASE_ADDR 0xBC000000
/*!
* This macro defines the physical to virtual address mapping for all the
* peripheral modules. It is used by passing in the physical address as x
* and returning the virtual address. If the physical address is not mapped,
* it returns 0xDEADBEEF
*/
#define IO_ADDRESS(x) \
(((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
0xDEADBEEF)
/*
* define the address mapping macros: in physical address order
*/
#define IRAM_IO_ADDRESS(x) \
(((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT)
#define L2CC_IO_ADDRESS(x) \
(((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
#define AIPS1_IO_ADDRESS(x) \
(((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
#define SPBA0_IO_ADDRESS(x) \
(((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
#define AIPS2_IO_ADDRESS(x) \
(((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
#define ROMP_IO_ADDRESS(x) \
(((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
#define AVIC_IO_ADDRESS(x) \
(((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
#define CS4_IO_ADDRESS(x) \
(((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
#define X_MEMC_IO_ADDRESS(x) \
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
#define PCMCIA_IO_ADDRESS(x) \
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
/* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */
#define PHYS_OFFSET CSD0_BASE_ADDR
/*
* Interrupt numbers
*/
#define MXC_INT_PEN_ADS7843 0
#define MXC_INT_RESV1 1
#define MXC_INT_CS8900A 2
#define MXC_INT_I2C3 3
#define MXC_INT_I2C2 4
#define MXC_INT_MPEG4_ENCODER 5
#define MXC_INT_RTIC 6
#define MXC_INT_FIRI 7
#define MXC_INT_MMC_SDHC2 8
#define MXC_INT_MMC_SDHC1 9
#define MXC_INT_I2C 10
#define MXC_INT_SSI2 11
#define MXC_INT_SSI1 12
#define MXC_INT_CSPI2 13
#define MXC_INT_CSPI1 14
#define MXC_INT_ATA 15
#define MXC_INT_MBX 16
#define MXC_INT_CSPI3 17
#define MXC_INT_UART3 18
#define MXC_INT_IIM 19
#define MXC_INT_SIM2 20
#define MXC_INT_SIM1 21
#define MXC_INT_RNGA 22
#define MXC_INT_EVTMON 23
#define MXC_INT_KPP 24
#define MXC_INT_RTC 25
#define MXC_INT_PWM 26
#define MXC_INT_EPIT2 27
#define MXC_INT_EPIT1 28
#define MXC_INT_GPT 29
#define MXC_INT_RESV30 30
#define MXC_INT_RESV31 31
#define MXC_INT_UART2 32
#define MXC_INT_NANDFC 33
#define MXC_INT_SDMA 34
#define MXC_INT_USB1 35
#define MXC_INT_USB2 36
#define MXC_INT_USB3 37
#define MXC_INT_USB4 38
#define MXC_INT_MSHC1 39
#define MXC_INT_MSHC2 40
#define MXC_INT_IPU_ERR 41
#define MXC_INT_IPU_SYN 42
#define MXC_INT_RESV43 43
#define MXC_INT_RESV44 44
#define MXC_INT_UART1 45
#define MXC_INT_UART4 46
#define MXC_INT_UART5 47
#define MXC_INT_ECT 48
#define MXC_INT_SCC_SCM 49
#define MXC_INT_SCC_SMN 50
#define MXC_INT_GPIO2 51
#define MXC_INT_GPIO1 52
#define MXC_INT_CCM 53
#define MXC_INT_PCMCIA 54
#define MXC_INT_WDOG 55
#define MXC_INT_GPIO3 56
#define MXC_INT_RESV57 57
#define MXC_INT_EXT_POWER 58
#define MXC_INT_EXT_TEMPER 59
#define MXC_INT_EXT_SENSOR60 60
#define MXC_INT_EXT_SENSOR61 61
#define MXC_INT_EXT_WDOG 62
#define MXC_INT_EXT_TV 63
#define MXC_MAX_INT_LINES 64
#define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES
/*!
* Number of GPIO port as defined in the IC Spec
*/
#define GPIO_PORT_NUM 3
/*!
* Number of GPIO pins per port
*/
#define GPIO_NUM_PIN 32
#define PROD_SIGNATURE 0x1 /* For MX31 */
#define SYSTEM_REV_MIN CHIP_REV_1_0
#define SYSTEM_REV_NUM 3
#endif /* __ASM_ARCH_MXC_MX31_H__ */

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/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MXC_H__
#define __ASM_ARCH_MXC_H__
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif
/*
*****************************************
* GPT Register definitions *
*****************************************
*/
#define MXC_GPT_GPTCR IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
#define MXC_GPT_GPTPR IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
#define MXC_GPT_GPTSR IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
#define MXC_GPT_GPTIR IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
#define MXC_GPT_GPTOCR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
#define MXC_GPT_GPTOCR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
#define MXC_GPT_GPTOCR3 IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
#define MXC_GPT_GPTICR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
/*!
* GPT Control register bit definitions
*/
#define GPTCR_FO3 (1 << 31)
#define GPTCR_FO2 (1 << 30)
#define GPTCR_FO1 (1 << 29)
#define GPTCR_OM3_SHIFT 26
#define GPTCR_OM3_MASK (7 << GPTCR_OM3_SHIFT)
#define GPTCR_OM3_DISCONNECTED (0 << GPTCR_OM3_SHIFT)
#define GPTCR_OM3_TOGGLE (1 << GPTCR_OM3_SHIFT)
#define GPTCR_OM3_CLEAR (2 << GPTCR_OM3_SHIFT)
#define GPTCR_OM3_SET (3 << GPTCR_OM3_SHIFT)
#define GPTCR_OM3_GENERATE_LOW (7 << GPTCR_OM3_SHIFT)
#define GPTCR_OM2_SHIFT 23
#define GPTCR_OM2_MASK (7 << GPTCR_OM2_SHIFT)
#define GPTCR_OM2_DISCONNECTED (0 << GPTCR_OM2_SHIFT)
#define GPTCR_OM2_TOGGLE (1 << GPTCR_OM2_SHIFT)
#define GPTCR_OM2_CLEAR (2 << GPTCR_OM2_SHIFT)
#define GPTCR_OM2_SET (3 << GPTCR_OM2_SHIFT)
#define GPTCR_OM2_GENERATE_LOW (7 << GPTCR_OM2_SHIFT)
#define GPTCR_OM1_SHIFT 20
#define GPTCR_OM1_MASK (7 << GPTCR_OM1_SHIFT)
#define GPTCR_OM1_DISCONNECTED (0 << GPTCR_OM1_SHIFT)
#define GPTCR_OM1_TOGGLE (1 << GPTCR_OM1_SHIFT)
#define GPTCR_OM1_CLEAR (2 << GPTCR_OM1_SHIFT)
#define GPTCR_OM1_SET (3 << GPTCR_OM1_SHIFT)
#define GPTCR_OM1_GENERATE_LOW (7 << GPTCR_OM1_SHIFT)
#define GPTCR_IM2_SHIFT 18
#define GPTCR_IM2_MASK (3 << GPTCR_IM2_SHIFT)
#define GPTCR_IM2_CAPTURE_DISABLE (0 << GPTCR_IM2_SHIFT)
#define GPTCR_IM2_CAPTURE_RISING (1 << GPTCR_IM2_SHIFT)
#define GPTCR_IM2_CAPTURE_FALLING (2 << GPTCR_IM2_SHIFT)
#define GPTCR_IM2_CAPTURE_BOTH (3 << GPTCR_IM2_SHIFT)
#define GPTCR_IM1_SHIFT 16
#define GPTCR_IM1_MASK (3 << GPTCR_IM1_SHIFT)
#define GPTCR_IM1_CAPTURE_DISABLE (0 << GPTCR_IM1_SHIFT)
#define GPTCR_IM1_CAPTURE_RISING (1 << GPTCR_IM1_SHIFT)
#define GPTCR_IM1_CAPTURE_FALLING (2 << GPTCR_IM1_SHIFT)
#define GPTCR_IM1_CAPTURE_BOTH (3 << GPTCR_IM1_SHIFT)
#define GPTCR_SWR (1 << 15)
#define GPTCR_FRR (1 << 9)
#define GPTCR_CLKSRC_SHIFT 6
#define GPTCR_CLKSRC_MASK (7 << GPTCR_CLKSRC_SHIFT)
#define GPTCR_CLKSRC_NOCLOCK (0 << GPTCR_CLKSRC_SHIFT)
#define GPTCR_CLKSRC_HIGHFREQ (2 << GPTCR_CLKSRC_SHIFT)
#define GPTCR_CLKSRC_CLKIN (3 << GPTCR_CLKSRC_SHIFT)
#define GPTCR_CLKSRC_CLK32K (7 << GPTCR_CLKSRC_SHIFT)
#define GPTCR_STOPEN (1 << 5)
#define GPTCR_DOZEN (1 << 4)
#define GPTCR_WAITEN (1 << 3)
#define GPTCR_DBGEN (1 << 2)
#define GPTCR_ENMOD (1 << 1)
#define GPTCR_ENABLE (1 << 0)
#define GPTSR_OF1 (1 << 0)
#define GPTSR_OF2 (1 << 1)
#define GPTSR_OF3 (1 << 2)
#define GPTSR_IF1 (1 << 3)
#define GPTSR_IF2 (1 << 4)
#define GPTSR_ROV (1 << 5)
#define GPTIR_OF1IE GPTSR_OF1
#define GPTIR_OF2IE GPTSR_OF2
#define GPTIR_OF3IE GPTSR_OF3
#define GPTIR_IF1IE GPTSR_IF1
#define GPTIR_IF2IE GPTSR_IF2
#define GPTIR_ROVIE GPTSR_ROV
/*
*****************************************
* AVIC Registers *
*****************************************
*/
#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
#define IIM_PROD_REV_SH 3
#define IIM_PROD_REV_LEN 5
#endif /* __ASM_ARCH_MXC_H__ */

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/*
* Copyright (C) 1999 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MXC_SYSTEM_H__
#define __ASM_ARCH_MXC_SYSTEM_H__
/*!
* @file system.h
* @brief This file contains idle and reset functions.
*
* @ingroup System
*/
/*!
* This function puts the CPU into idle mode. It is called by default_idle()
* in process.c file.
*/
static inline void arch_idle(void)
{
cpu_do_idle();
}
/*
* This function resets the system. It is called by machine_restart().
*
* @param mode indicates different kinds of resets
*/
static inline void arch_reset(char mode)
{
cpu_reset(0);
}
#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */

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/*
* Copyright (C) 1999 ARM Limited
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MXC_TIMEX_H__
#define __ASM_ARCH_MXC_TIMEX_H__
#include <asm/hardware.h> /* for CLOCK_TICK_RATE */
#endif /* __ASM_ARCH_MXC_TIMEX_H__ */

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/*
* include/asm-arm/arch-mxc/uncompress.h
*
*
*
* Copyright (C) 1999 ARM Limited
* Copyright (C) Shane Nay (shane@minirl.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
#define __ASM_ARCH_MXC_UNCOMPRESS_H__
#define __MXC_BOOT_UNCOMPRESS
#include <asm/hardware.h>
#include <asm/processor.h>
#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
#define USR2 0x98
#define USR2_TXFE (1<<14)
#define TXR 0x40
#define UCR1 0x80
#define UCR1_UARTEN 1
/*
* The following code assumes the serial port has already been
* initialized by the bootloader. We search for the first enabled
* port in the most probable order. If you didn't setup a port in
* your bootloader then nothing will appear (which might be desired).
*
* This does not append a newline
*/
static void putc(int ch)
{
static unsigned long serial_port = 0;
if (unlikely(serial_port == 0)) {
do {
serial_port = UART1_BASE_ADDR;
if (UART(UCR1) & UCR1_UARTEN)
break;
serial_port = UART2_BASE_ADDR;
if (UART(UCR1) & UCR1_UARTEN)
break;
return;
} while (0);
}
while (!(UART(USR2) & USR2_TXFE))
cpu_relax();
UART(TXR) = ch;
}
#define flush() do { } while (0)
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()
#endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */

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/*
* Copyright (C) 2000 Russell King.
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MXC_VMALLOC_H__
#define __ASM_ARCH_MXC_VMALLOC_H__
/*!
* @file vmalloc.h
*
* @brief This file contains platform specific macros for vmalloc.
*
* @ingroup System
*/
/*!
* vmalloc ending address
*/
#define VMALLOC_END 0xF4000000
#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */