powerpc/usb: fix issue of CPU halt when missing USB PHY clock
when missing USB PHY clock, kernel booting up will halt during USB initialization. We should check USBGP[PHY_CLK_VALID] bit to avoid CPU hang in this case. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -239,7 +239,7 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
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ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
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}
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static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
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static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
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{
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struct usb_hcd *hcd = ehci_to_hcd(ehci);
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struct fsl_usb2_platform_data *pdata;
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@ -299,12 +299,19 @@ static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
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#endif
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out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
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}
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if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & CTRL_PHY_CLK_VALID)) {
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printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n");
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return -ENODEV;
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}
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return 0;
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}
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/* called after powerup, by probe or system-pm "wakeup" */
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static int ehci_fsl_reinit(struct ehci_hcd *ehci)
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{
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ehci_fsl_usb_setup(ehci);
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if (ehci_fsl_usb_setup(ehci))
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return -ENODEV;
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ehci_port_power(ehci, 0);
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return 0;
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@ -45,5 +45,6 @@
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#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
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#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
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#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
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#define CTRL_PHY_CLK_VALID (1 << 17)
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#define SNOOP_SIZE_2GB 0x1e
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#endif /* _EHCI_FSL_H */
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