drm/radeon: add proper checking of RESOLVE_BOX command for r600-r700
Checking of the second colorbuffer was skipped on r700, because CB_TARGET_MASK was 0xf. With r600, CB_TARGET_MASK is changed to 0xff, so we must set the number of samples of the second colorbuffer to 1 in order to pass the CS checker. The DRM version is bumped, because RESOLVE_BOX is always rejected without this fix on r600. Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák
Alex Deucher
parent
3b5ef597ec
commit
523885dec1
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@ -63,6 +63,7 @@ struct r600_cs_track {
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u32 cb_color_size_idx[8]; /* unused */
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u32 cb_target_mask;
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u32 cb_shader_mask; /* unused */
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bool is_resolve;
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u32 cb_color_size[8];
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u32 vgt_strmout_en;
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u32 vgt_strmout_buffer_en;
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@ -321,6 +322,7 @@ static void r600_cs_track_init(struct r600_cs_track *track)
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track->cb_color_tile_offset[i] = 0xFFFFFFFF;
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track->cb_color_mask[i] = 0xFFFFFFFF;
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}
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track->is_resolve = false;
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track->nsamples = 16;
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track->log_nsamples = 4;
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track->cb_target_mask = 0xFFFFFFFF;
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@ -359,6 +361,8 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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volatile u32 *ib = p->ib.ptr;
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unsigned array_mode;
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u32 format;
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/* When resolve is used, the second colorbuffer has always 1 sample. */
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unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
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size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
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format = G_0280A0_FORMAT(track->cb_color_info[i]);
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@ -382,7 +386,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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array_check.group_size = track->group_size;
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array_check.nbanks = track->nbanks;
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array_check.npipes = track->npipes;
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array_check.nsamples = track->nsamples;
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array_check.nsamples = nsamples;
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array_check.blocksize = r600_fmt_get_blocksize(format);
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if (r600_get_array_mode_alignment(&array_check,
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&pitch_align, &height_align, &depth_align, &base_align)) {
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@ -428,7 +432,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
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/* check offset */
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tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
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r600_fmt_get_blocksize(format) * track->nsamples;
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r600_fmt_get_blocksize(format) * nsamples;
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switch (array_mode) {
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default:
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case V_0280A0_ARRAY_LINEAR_GENERAL:
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@ -799,6 +803,12 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
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*/
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if (track->cb_dirty) {
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tmp = track->cb_target_mask;
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/* We must check both colorbuffers for RESOLVE. */
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if (track->is_resolve) {
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tmp |= 0xff;
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}
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for (i = 0; i < 8; i++) {
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if ((tmp >> (i * 4)) & 0xF) {
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/* at least one component is enabled */
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@ -1288,6 +1298,11 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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track->nsamples = 1 << tmp;
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track->cb_dirty = true;
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break;
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case R_028808_CB_COLOR_CONTROL:
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tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
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track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
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track->cb_dirty = true;
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break;
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case R_0280A0_CB_COLOR0_INFO:
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case R_0280A4_CB_COLOR1_INFO:
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case R_0280A8_CB_COLOR2_INFO:
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@ -66,6 +66,14 @@
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#define CC_RB_BACKEND_DISABLE 0x98F4
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#define BACKEND_DISABLE(x) ((x) << 16)
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#define R_028808_CB_COLOR_CONTROL 0x28808
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#define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4)
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#define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7)
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#define C_028808_SPECIAL_OP 0xFFFFFF8F
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#define V_028808_SPECIAL_NORMAL 0x00
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#define V_028808_SPECIAL_DISABLE 0x01
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#define V_028808_SPECIAL_RESOLVE_BOX 0x07
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#define CB_COLOR0_BASE 0x28040
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#define CB_COLOR1_BASE 0x28044
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#define CB_COLOR2_BASE 0x28048
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@ -63,9 +63,10 @@
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* 2.19.0 - r600-eg: MSAA textures
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* 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
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* 2.21.0 - r600-r700: FMASK and CMASK
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* 2.22.0 - r600 only: RESOLVE_BOX allowed
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*/
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#define KMS_DRIVER_MAJOR 2
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#define KMS_DRIVER_MINOR 21
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#define KMS_DRIVER_MINOR 22
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#define KMS_DRIVER_PATCHLEVEL 0
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int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
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int radeon_driver_unload_kms(struct drm_device *dev);
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@ -744,7 +744,6 @@ r600 0x9400
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0x00028C38 CB_CLRCMP_DST
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0x00028C3C CB_CLRCMP_MSK
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0x00028C34 CB_CLRCMP_SRC
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0x00028808 CB_COLOR_CONTROL
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0x0002842C CB_FOG_BLUE
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0x00028428 CB_FOG_GREEN
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0x00028424 CB_FOG_RED
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