MIPS: devicetree: fix cpu interrupt controller node-names

Here is the quote from [1]:

    The unit-address must match the first address specified
    in the reg property of the node. If the node has no reg property,
    the @ and unit-address must be omitted and the node-name alone
    differentiates the node from other nodes at the same level

This patch adjusts MIPS dts-files and devicetree binding
documentation in accordance with [1].

    [1] Power.org(tm) Standard for Embedded Power Architecture(tm)
        Platform Requirements (ePAPR). Version 1.1 – 08 April 2011.
        Chapter 2.2.1.1 Node Name Requirements

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13345/
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Antony Pavlov 2016-05-23 14:39:00 +03:00 committed by Ralf Baechle
parent 94cc36b84a
commit 5214cae77c
7 changed files with 7 additions and 7 deletions

View File

@ -13,7 +13,7 @@ Required properties:
- compatible : Should be "mti,cpu-interrupt-controller" - compatible : Should be "mti,cpu-interrupt-controller"
Example devicetree: Example devicetree:
cpu-irq: cpu-irq@0 { cpu-irq: cpu-irq {
#address-cells = <0>; #address-cells = <0>;
interrupt-controller; interrupt-controller;

View File

@ -5,7 +5,7 @@
#size-cells = <1>; #size-cells = <1>;
compatible = "ingenic,jz4740"; compatible = "ingenic,jz4740";
cpuintc: interrupt-controller@0 { cpuintc: interrupt-controller {
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-controller; interrupt-controller;

View File

@ -9,7 +9,7 @@
}; };
}; };
cpuintc: cpuintc@0 { cpuintc: cpuintc {
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-controller; interrupt-controller;

View File

@ -9,7 +9,7 @@
}; };
}; };
cpuintc: cpuintc@0 { cpuintc: cpuintc {
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-controller; interrupt-controller;

View File

@ -9,7 +9,7 @@
}; };
}; };
cpuintc: cpuintc@0 { cpuintc: cpuintc {
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-controller; interrupt-controller;

View File

@ -9,7 +9,7 @@
}; };
}; };
cpuintc: cpuintc@0 { cpuintc: cpuintc {
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-controller; interrupt-controller;

View File

@ -10,7 +10,7 @@
reg = <0x0 0x08000000>; reg = <0x0 0x08000000>;
}; };
cpuintc: interrupt-controller@0 { cpuintc: interrupt-controller {
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-controller; interrupt-controller;