usb: isp1760: Initialize the bus interface in core code
Although the corresponding register is part of the HCD register space, processor bus initialization is not specific to the HCD. To prepare for device controller support, move bus interface initialization to core code. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Laurent Pinchart
Felipe Balbi
parent
667c45c2f1
commit
5171446a3a
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@ -13,7 +13,8 @@
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* version 2 as published by the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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@ -22,6 +23,54 @@
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#include "isp1760-core.h"
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#include "isp1760-hcd.h"
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#include "isp1760-regs.h"
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static void isp1760_init_core(struct isp1760_device *isp)
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{
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u32 hwmode;
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/* Low-level chip reset */
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if (isp->rst_gpio) {
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gpiod_set_value_cansleep(isp->rst_gpio, 1);
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mdelay(50);
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gpiod_set_value_cansleep(isp->rst_gpio, 0);
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}
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/*
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* Reset the host controller, including the CPU interface
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* configuration.
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*/
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isp1760_write32(isp->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
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msleep(100);
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/* Setup HW Mode Control: This assumes a level active-low interrupt */
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hwmode = HW_DATA_BUS_32BIT;
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if (isp->devflags & ISP1760_FLAG_BUS_WIDTH_16)
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hwmode &= ~HW_DATA_BUS_32BIT;
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if (isp->devflags & ISP1760_FLAG_ANALOG_OC)
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hwmode |= HW_ANA_DIGI_OC;
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if (isp->devflags & ISP1760_FLAG_DACK_POL_HIGH)
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hwmode |= HW_DACK_POL_HIGH;
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if (isp->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
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hwmode |= HW_DREQ_POL_HIGH;
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if (isp->devflags & ISP1760_FLAG_INTR_POL_HIGH)
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hwmode |= HW_INTR_HIGH_ACT;
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if (isp->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
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hwmode |= HW_INTR_EDGE_TRIG;
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/*
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* We have to set this first in case we're in 16-bit mode.
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* Write it twice to ensure correct upper bits if switching
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* to 16-bit mode.
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*/
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isp1760_write32(isp->regs, HC_HW_MODE_CTRL, hwmode);
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isp1760_write32(isp->regs, HC_HW_MODE_CTRL, hwmode);
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dev_info(isp->dev, "bus width: %u, oc: %s\n",
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isp->devflags & ISP1760_FLAG_BUS_WIDTH_16 ? 16 : 32,
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isp->devflags & ISP1760_FLAG_ANALOG_OC ? "analog" : "digital");
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}
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int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
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struct device *dev, unsigned int devflags)
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@ -39,12 +88,21 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
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if (!isp)
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return -ENOMEM;
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isp->dev = dev;
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isp->devflags = devflags;
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isp->rst_gpio = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
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if (IS_ERR(isp->rst_gpio))
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return PTR_ERR(isp->rst_gpio);
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isp->regs = devm_ioremap_resource(dev, mem);
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if (IS_ERR(isp->regs))
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return PTR_ERR(isp->regs);
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isp1760_init_core(isp);
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ret = isp1760_hcd_register(&isp->hcd, isp->regs, mem, irq,
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irqflags | IRQF_SHARED, dev, devflags);
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irqflags | IRQF_SHARED, dev);
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if (ret < 0)
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return ret;
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@ -20,8 +20,29 @@
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#include "isp1760-hcd.h"
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struct device;
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struct gpio_desc;
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/*
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* Device flags that can vary from board to board. All of these
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* indicate the most "atypical" case, so that a devflags of 0 is
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* a sane default configuration.
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*/
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#define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */
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#define ISP1760_FLAG_OTG_EN 0x00000004 /* Port 1 supports OTG */
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#define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */
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#define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */
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#define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */
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#define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */
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#define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */
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#define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */
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struct isp1760_device {
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struct device *dev;
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void __iomem *regs;
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unsigned int devflags;
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struct gpio_desc *rst_gpio;
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struct isp1760_hcd hcd;
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};
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@ -30,4 +51,14 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
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struct device *dev, unsigned int devflags);
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void isp1760_unregister(struct device *dev);
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static inline u32 isp1760_read32(void __iomem *base, u32 reg)
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{
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return readl(base + reg);
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}
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static inline void isp1760_write32(void __iomem *base, u32 reg, u32 val)
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{
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writel(val, base + reg);
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}
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#endif
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@ -26,6 +26,7 @@
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#include <asm/unaligned.h>
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#include <asm/cacheflush.h>
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#include "isp1760-core.h"
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#include "isp1760-hcd.h"
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#include "isp1760-regs.h"
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@ -160,12 +161,12 @@ struct urb_listitem {
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*/
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static u32 reg_read32(void __iomem *base, u32 reg)
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{
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return readl(base + reg);
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return isp1760_read32(base, reg);
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}
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static void reg_write32(void __iomem *base, u32 reg, u32 val)
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{
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writel(val, base + reg);
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isp1760_write32(base, reg, val);
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}
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/*
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@ -466,37 +467,6 @@ static int isp1760_hc_setup(struct usb_hcd *hcd)
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int result;
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u32 scratch, hwmode;
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/* low-level chip reset */
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if (priv->rst_gpio) {
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gpiod_set_value_cansleep(priv->rst_gpio, 1);
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mdelay(50);
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gpiod_set_value_cansleep(priv->rst_gpio, 0);
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}
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/* Setup HW Mode Control: This assumes a level active-low interrupt */
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hwmode = HW_DATA_BUS_32BIT;
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if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
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hwmode &= ~HW_DATA_BUS_32BIT;
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if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
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hwmode |= HW_ANA_DIGI_OC;
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if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
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hwmode |= HW_DACK_POL_HIGH;
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if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
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hwmode |= HW_DREQ_POL_HIGH;
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if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
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hwmode |= HW_INTR_HIGH_ACT;
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if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
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hwmode |= HW_INTR_EDGE_TRIG;
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/*
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* We have to set this first in case we're in 16-bit mode.
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* Write it twice to ensure correct upper bits if switching
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* to 16-bit mode.
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*/
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reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
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reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
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reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
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/* Change bus pattern */
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scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
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@ -506,31 +476,27 @@ static int isp1760_hc_setup(struct usb_hcd *hcd)
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return -ENODEV;
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}
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/* pre reset */
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/*
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* The RESET_HC bit in the SW_RESET register is supposed to reset the
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* host controller without touching the CPU interface registers, but at
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* least on the ISP1761 it seems to behave as the RESET_ALL bit and
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* reset the whole device. We thus can't use it here, so let's reset
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* the host controller through the EHCI USB Command register. The device
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* has been reset in core code anyway, so this shouldn't matter.
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*/
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reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
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reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
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reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
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reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
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/* reset */
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reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
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mdelay(100);
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reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
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mdelay(100);
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result = ehci_reset(hcd);
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if (result)
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return result;
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/* Step 11 passed */
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dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
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(priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
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16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
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"analog" : "digital");
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/* ATL reset */
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hwmode = reg_read32(hcd->regs, HC_HW_MODE_CTRL) & ~ALL_ATX_RESET;
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reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
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mdelay(10);
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reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
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@ -2234,7 +2200,7 @@ void isp1760_deinit_kmem_cache(void)
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int isp1760_hcd_register(struct isp1760_hcd *priv, void __iomem *regs,
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struct resource *mem, int irq, unsigned long irqflags,
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struct device *dev, unsigned int devflags)
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struct device *dev)
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{
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struct usb_hcd *hcd;
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int ret;
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@ -2246,13 +2212,6 @@ int isp1760_hcd_register(struct isp1760_hcd *priv, void __iomem *regs,
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*(struct isp1760_hcd **)hcd->hcd_priv = priv;
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priv->hcd = hcd;
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priv->devflags = devflags;
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priv->rst_gpio = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
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if (IS_ERR(priv->rst_gpio)) {
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ret = PTR_ERR(priv->rst_gpio);
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goto error;
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}
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init_memory(priv);
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@ -3,7 +3,6 @@
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#include <linux/spinlock.h>
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struct gpio_desc;
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struct isp1760_qh;
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struct isp1760_qtd;
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struct resource;
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@ -27,20 +26,6 @@ struct usb_hcd;
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#define MAX_PAYLOAD_SIZE BLOCK_3_SIZE
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#define PAYLOAD_AREA_SIZE 0xf000
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/*
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* Device flags that can vary from board to board. All of these
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* indicate the most "atypical" case, so that a devflags of 0 is
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* a sane default configuration.
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*/
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#define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */
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#define ISP1760_FLAG_OTG_EN 0x00000004 /* Port 1 supports OTG */
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#define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */
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#define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */
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#define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */
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#define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */
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#define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */
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#define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */
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struct isp1760_slotinfo {
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struct isp1760_qh *qh;
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struct isp1760_qtd *qtd;
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@ -79,14 +64,11 @@ struct isp1760_hcd {
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unsigned i_thresh;
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unsigned long reset_done;
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unsigned long next_statechange;
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unsigned int devflags;
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struct gpio_desc *rst_gpio;
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};
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int isp1760_hcd_register(struct isp1760_hcd *priv, void __iomem *regs,
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struct resource *mem, int irq, unsigned long irqflags,
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struct device *dev, unsigned int devflags);
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struct device *dev);
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void isp1760_hcd_unregister(struct isp1760_hcd *priv);
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int isp1760_init_kmem_once(void);
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