media: camss: csiphy: Split to hardware dependent and independent parts
This will allow to add support for different hardware. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> [hans.verkuil@cisco.com: remove trailing empty line] Signed-off-by: Hans Verkuil <hansverk@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
This commit is contained in:
Todor Tomov
Mauro Carvalho Chehab
parent
02afa816db
commit
516e8f0f89
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@ -3,6 +3,7 @@
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qcom-camss-objs += \
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camss.o \
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camss-csid.o \
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camss-csiphy-2ph-1-0.o \
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camss-csiphy.o \
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camss-ispif.o \
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camss-vfe.o \
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@ -0,0 +1,172 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* camss-csiphy-2ph-1-0.c
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*
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* Qualcomm MSM Camera Subsystem - CSIPHY Module 2phase v1.0
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*
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* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
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* Copyright (C) 2016-2018 Linaro Ltd.
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*/
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#include "camss-csiphy.h"
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#define CAMSS_CSI_PHY_LNn_CFG2(n) (0x004 + 0x40 * (n))
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#define CAMSS_CSI_PHY_LNn_CFG3(n) (0x008 + 0x40 * (n))
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#define CAMSS_CSI_PHY_GLBL_RESET 0x140
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#define CAMSS_CSI_PHY_GLBL_PWR_CFG 0x144
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#define CAMSS_CSI_PHY_GLBL_IRQ_CMD 0x164
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#define CAMSS_CSI_PHY_HW_VERSION 0x188
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#define CAMSS_CSI_PHY_INTERRUPT_STATUSn(n) (0x18c + 0x4 * (n))
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#define CAMSS_CSI_PHY_INTERRUPT_MASKn(n) (0x1ac + 0x4 * (n))
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#define CAMSS_CSI_PHY_INTERRUPT_CLEARn(n) (0x1cc + 0x4 * (n))
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#define CAMSS_CSI_PHY_GLBL_T_INIT_CFG0 0x1ec
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#define CAMSS_CSI_PHY_T_WAKEUP_CFG0 0x1f4
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static void csiphy_hw_version_read(struct csiphy_device *csiphy,
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struct device *dev)
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{
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u8 hw_version = readl_relaxed(csiphy->base +
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CAMSS_CSI_PHY_HW_VERSION);
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dev_dbg(dev, "CSIPHY HW Version = 0x%02x\n", hw_version);
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}
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/*
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* csiphy_reset - Perform software reset on CSIPHY module
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* @csiphy: CSIPHY device
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*/
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static void csiphy_reset(struct csiphy_device *csiphy)
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{
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writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
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usleep_range(5000, 8000);
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writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
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}
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/*
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* csiphy_settle_cnt_calc - Calculate settle count value
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*
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* Helper function to calculate settle count value. This is
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* based on the CSI2 T_hs_settle parameter which in turn
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* is calculated based on the CSI2 transmitter pixel clock
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* frequency.
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*
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* Return settle count value or 0 if the CSI2 pixel clock
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* frequency is not available
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*/
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static u8 csiphy_settle_cnt_calc(u32 pixel_clock, u8 bpp, u8 num_lanes,
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u32 timer_clk_rate)
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{
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u32 mipi_clock; /* Hz */
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u32 ui; /* ps */
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u32 timer_period; /* ps */
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u32 t_hs_prepare_max; /* ps */
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u32 t_hs_prepare_zero_min; /* ps */
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u32 t_hs_settle; /* ps */
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u8 settle_cnt;
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mipi_clock = pixel_clock * bpp / (2 * num_lanes);
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ui = div_u64(1000000000000LL, mipi_clock);
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ui /= 2;
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t_hs_prepare_max = 85000 + 6 * ui;
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t_hs_prepare_zero_min = 145000 + 10 * ui;
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t_hs_settle = (t_hs_prepare_max + t_hs_prepare_zero_min) / 2;
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timer_period = div_u64(1000000000000LL, timer_clk_rate);
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settle_cnt = t_hs_settle / timer_period - 1;
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return settle_cnt;
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}
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static void csiphy_lanes_enable(struct csiphy_device *csiphy,
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struct csiphy_config *cfg,
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u32 pixel_clock, u8 bpp, u8 lane_mask)
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{
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struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
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u8 settle_cnt;
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u8 val;
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int i = 0;
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settle_cnt = csiphy_settle_cnt_calc(pixel_clock, bpp, c->num_data,
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csiphy->timer_clk_rate);
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writel_relaxed(0x1, csiphy->base +
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CAMSS_CSI_PHY_GLBL_T_INIT_CFG0);
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writel_relaxed(0x1, csiphy->base +
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CAMSS_CSI_PHY_T_WAKEUP_CFG0);
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val = 0x1;
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val |= lane_mask << 1;
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writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);
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val = cfg->combo_mode << 4;
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writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
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while (lane_mask) {
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if (lane_mask & 0x1) {
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writel_relaxed(0x10, csiphy->base +
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CAMSS_CSI_PHY_LNn_CFG2(i));
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writel_relaxed(settle_cnt, csiphy->base +
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CAMSS_CSI_PHY_LNn_CFG3(i));
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writel_relaxed(0x3f, csiphy->base +
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CAMSS_CSI_PHY_INTERRUPT_MASKn(i));
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writel_relaxed(0x3f, csiphy->base +
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CAMSS_CSI_PHY_INTERRUPT_CLEARn(i));
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}
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lane_mask >>= 1;
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i++;
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}
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}
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static void csiphy_lanes_disable(struct csiphy_device *csiphy, u8 lane_mask)
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{
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int i = 0;
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while (lane_mask) {
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if (lane_mask & 0x1)
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writel_relaxed(0x0, csiphy->base +
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CAMSS_CSI_PHY_LNn_CFG2(i));
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lane_mask >>= 1;
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i++;
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}
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writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);
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}
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/*
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* csiphy_isr - CSIPHY module interrupt handler
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* @irq: Interrupt line
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* @dev: CSIPHY device
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*
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* Return IRQ_HANDLED on success
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*/
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static irqreturn_t csiphy_isr(int irq, void *dev)
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{
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struct csiphy_device *csiphy = dev;
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u8 i;
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for (i = 0; i < 8; i++) {
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u8 val = readl_relaxed(csiphy->base +
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CAMSS_CSI_PHY_INTERRUPT_STATUSn(i));
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writel_relaxed(val, csiphy->base +
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CAMSS_CSI_PHY_INTERRUPT_CLEARn(i));
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writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD);
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writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD);
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writel_relaxed(0x0, csiphy->base +
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CAMSS_CSI_PHY_INTERRUPT_CLEARn(i));
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}
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return IRQ_HANDLED;
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}
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const struct csiphy_hw_ops csiphy_ops_2ph_1_0 = {
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.hw_version_read = csiphy_hw_version_read,
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.reset = csiphy_reset,
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.lanes_enable = csiphy_lanes_enable,
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.lanes_disable = csiphy_lanes_disable,
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.isr = csiphy_isr,
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};
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@ -23,18 +23,6 @@
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#define MSM_CSIPHY_NAME "msm_csiphy"
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#define CAMSS_CSI_PHY_LNn_CFG2(n) (0x004 + 0x40 * (n))
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#define CAMSS_CSI_PHY_LNn_CFG3(n) (0x008 + 0x40 * (n))
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#define CAMSS_CSI_PHY_GLBL_RESET 0x140
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#define CAMSS_CSI_PHY_GLBL_PWR_CFG 0x144
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#define CAMSS_CSI_PHY_GLBL_IRQ_CMD 0x164
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#define CAMSS_CSI_PHY_HW_VERSION 0x188
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#define CAMSS_CSI_PHY_INTERRUPT_STATUSn(n) (0x18c + 0x4 * (n))
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#define CAMSS_CSI_PHY_INTERRUPT_MASKn(n) (0x1ac + 0x4 * (n))
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#define CAMSS_CSI_PHY_INTERRUPT_CLEARn(n) (0x1cc + 0x4 * (n))
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#define CAMSS_CSI_PHY_GLBL_T_INIT_CFG0 0x1ec
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#define CAMSS_CSI_PHY_T_WAKEUP_CFG0 0x1f4
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static const struct {
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u32 code;
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u8 bpp;
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@ -124,32 +112,6 @@ static u8 csiphy_get_bpp(u32 code)
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return csiphy_formats[0].bpp;
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}
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/*
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* csiphy_isr - CSIPHY module interrupt handler
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* @irq: Interrupt line
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* @dev: CSIPHY device
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*
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* Return IRQ_HANDLED on success
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*/
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static irqreturn_t csiphy_isr(int irq, void *dev)
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{
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struct csiphy_device *csiphy = dev;
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u8 i;
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for (i = 0; i < 8; i++) {
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u8 val = readl_relaxed(csiphy->base +
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CAMSS_CSI_PHY_INTERRUPT_STATUSn(i));
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writel_relaxed(val, csiphy->base +
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CAMSS_CSI_PHY_INTERRUPT_CLEARn(i));
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writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD);
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writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD);
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writel_relaxed(0x0, csiphy->base +
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CAMSS_CSI_PHY_INTERRUPT_CLEARn(i));
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}
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return IRQ_HANDLED;
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}
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/*
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* csiphy_set_clock_rates - Calculate and set clock rates on CSIPHY module
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* @csiphy: CSIPHY device
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@ -214,17 +176,6 @@ static int csiphy_set_clock_rates(struct csiphy_device *csiphy)
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return 0;
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}
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/*
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* csiphy_reset - Perform software reset on CSIPHY module
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* @csiphy: CSIPHY device
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*/
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static void csiphy_reset(struct csiphy_device *csiphy)
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{
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writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
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usleep_range(5000, 8000);
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writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
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}
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/*
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* csiphy_set_power - Power on/off CSIPHY module
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* @sd: CSIPHY V4L2 subdevice
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@ -238,7 +189,6 @@ static int csiphy_set_power(struct v4l2_subdev *sd, int on)
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struct device *dev = csiphy->camss->dev;
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if (on) {
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u8 hw_version;
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int ret;
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ret = pm_runtime_get_sync(dev);
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@ -259,11 +209,9 @@ static int csiphy_set_power(struct v4l2_subdev *sd, int on)
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enable_irq(csiphy->irq);
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csiphy_reset(csiphy);
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csiphy->ops->reset(csiphy);
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hw_version = readl_relaxed(csiphy->base +
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CAMSS_CSI_PHY_HW_VERSION);
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dev_dbg(dev, "CSIPHY HW Version = 0x%02x\n", hw_version);
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csiphy->ops->hw_version_read(csiphy, dev);
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} else {
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disable_irq(csiphy->irq);
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@ -294,58 +242,6 @@ static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg)
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return lane_mask;
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}
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/*
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* csiphy_settle_cnt_calc - Calculate settle count value
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* @csiphy: CSIPHY device
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*
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* Helper function to calculate settle count value. This is
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* based on the CSI2 T_hs_settle parameter which in turn
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* is calculated based on the CSI2 transmitter pixel clock
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* frequency.
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*
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* Return settle count value or 0 if the CSI2 pixel clock
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* frequency is not available
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*/
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static u8 csiphy_settle_cnt_calc(struct csiphy_device *csiphy)
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{
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u8 bpp = csiphy_get_bpp(
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csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
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u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data;
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u32 pixel_clock; /* Hz */
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u32 mipi_clock; /* Hz */
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u32 ui; /* ps */
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u32 timer_period; /* ps */
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u32 t_hs_prepare_max; /* ps */
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u32 t_hs_prepare_zero_min; /* ps */
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u32 t_hs_settle; /* ps */
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u8 settle_cnt;
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int ret;
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ret = camss_get_pixel_clock(&csiphy->subdev.entity, &pixel_clock);
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if (ret) {
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dev_err(csiphy->camss->dev,
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"Cannot get CSI2 transmitter's pixel clock\n");
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return 0;
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}
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if (!pixel_clock) {
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dev_err(csiphy->camss->dev,
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"Got pixel clock == 0, cannot continue\n");
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return 0;
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}
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mipi_clock = pixel_clock * bpp / (2 * num_lanes);
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ui = div_u64(1000000000000LL, mipi_clock);
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ui /= 2;
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t_hs_prepare_max = 85000 + 6 * ui;
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t_hs_prepare_zero_min = 145000 + 10 * ui;
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t_hs_settle = (t_hs_prepare_max + t_hs_prepare_zero_min) / 2;
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timer_period = div_u64(1000000000000LL, csiphy->timer_clk_rate);
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settle_cnt = t_hs_settle / timer_period - 1;
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return settle_cnt;
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}
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/*
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* csiphy_stream_on - Enable streaming on CSIPHY module
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* @csiphy: CSIPHY device
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@ -358,14 +254,23 @@ static u8 csiphy_settle_cnt_calc(struct csiphy_device *csiphy)
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static int csiphy_stream_on(struct csiphy_device *csiphy)
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{
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struct csiphy_config *cfg = &csiphy->cfg;
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u32 pixel_clock;
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u8 lane_mask = csiphy_get_lane_mask(&cfg->csi2->lane_cfg);
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u8 settle_cnt;
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u8 bpp = csiphy_get_bpp(csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
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u8 val;
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int i = 0;
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int ret;
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settle_cnt = csiphy_settle_cnt_calc(csiphy);
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if (!settle_cnt)
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ret = camss_get_pixel_clock(&csiphy->subdev.entity, &pixel_clock);
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if (ret) {
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dev_err(csiphy->camss->dev,
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"Cannot get CSI2 transmitter's pixel clock\n");
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return -EINVAL;
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}
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if (!pixel_clock) {
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dev_err(csiphy->camss->dev,
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"Got pixel clock == 0, cannot continue\n");
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return -EINVAL;
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}
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val = readl_relaxed(csiphy->base_clk_mux);
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if (cfg->combo_mode && (lane_mask & 0x18) == 0x18) {
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@ -378,33 +283,7 @@ static int csiphy_stream_on(struct csiphy_device *csiphy)
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writel_relaxed(val, csiphy->base_clk_mux);
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wmb();
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writel_relaxed(0x1, csiphy->base +
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CAMSS_CSI_PHY_GLBL_T_INIT_CFG0);
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writel_relaxed(0x1, csiphy->base +
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CAMSS_CSI_PHY_T_WAKEUP_CFG0);
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val = 0x1;
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val |= lane_mask << 1;
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writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);
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val = cfg->combo_mode << 4;
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writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
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while (lane_mask) {
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if (lane_mask & 0x1) {
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writel_relaxed(0x10, csiphy->base +
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CAMSS_CSI_PHY_LNn_CFG2(i));
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writel_relaxed(settle_cnt, csiphy->base +
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CAMSS_CSI_PHY_LNn_CFG3(i));
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writel_relaxed(0x3f, csiphy->base +
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CAMSS_CSI_PHY_INTERRUPT_MASKn(i));
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writel_relaxed(0x3f, csiphy->base +
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CAMSS_CSI_PHY_INTERRUPT_CLEARn(i));
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}
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lane_mask >>= 1;
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i++;
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}
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csiphy->ops->lanes_enable(csiphy, cfg, pixel_clock, bpp, lane_mask);
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return 0;
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}
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@ -418,18 +297,8 @@ static int csiphy_stream_on(struct csiphy_device *csiphy)
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static void csiphy_stream_off(struct csiphy_device *csiphy)
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{
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u8 lane_mask = csiphy_get_lane_mask(&csiphy->cfg.csi2->lane_cfg);
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int i = 0;
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while (lane_mask) {
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if (lane_mask & 0x1)
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writel_relaxed(0x0, csiphy->base +
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CAMSS_CSI_PHY_LNn_CFG2(i));
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lane_mask >>= 1;
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i++;
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}
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writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);
|
||||
csiphy->ops->lanes_disable(csiphy, lane_mask);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -696,6 +565,11 @@ int msm_csiphy_subdev_init(struct camss *camss,
|
|||
csiphy->id = id;
|
||||
csiphy->cfg.combo_mode = 0;
|
||||
|
||||
if (camss->version == CAMSS_8x16)
|
||||
csiphy->ops = &csiphy_ops_2ph_1_0;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
/* Memory */
|
||||
|
||||
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]);
|
||||
|
|
@ -724,7 +598,8 @@ int msm_csiphy_subdev_init(struct camss *camss,
|
|||
csiphy->irq = r->start;
|
||||
snprintf(csiphy->irq_name, sizeof(csiphy->irq_name), "%s_%s%d",
|
||||
dev_name(dev), MSM_CSIPHY_NAME, csiphy->id);
|
||||
ret = devm_request_irq(dev, csiphy->irq, csiphy_isr,
|
||||
|
||||
ret = devm_request_irq(dev, csiphy->irq, csiphy->ops->isr,
|
||||
IRQF_TRIGGER_RISING, csiphy->irq_name, csiphy);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "request_irq failed: %d\n", ret);
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#define QC_MSM_CAMSS_CSIPHY_H
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <media/media-entity.h>
|
||||
#include <media/v4l2-device.h>
|
||||
#include <media/v4l2-mediabus.h>
|
||||
|
|
@ -41,6 +42,19 @@ struct csiphy_config {
|
|||
struct csiphy_csi2_cfg *csi2;
|
||||
};
|
||||
|
||||
struct csiphy_device;
|
||||
|
||||
struct csiphy_hw_ops {
|
||||
void (*hw_version_read)(struct csiphy_device *csiphy,
|
||||
struct device *dev);
|
||||
void (*reset)(struct csiphy_device *csiphy);
|
||||
void (*lanes_enable)(struct csiphy_device *csiphy,
|
||||
struct csiphy_config *cfg,
|
||||
u32 pixel_clock, u8 bpp, u8 lane_mask);
|
||||
void (*lanes_disable)(struct csiphy_device *csiphy, u8 lane_mask);
|
||||
irqreturn_t (*isr)(int irq, void *dev);
|
||||
};
|
||||
|
||||
struct csiphy_device {
|
||||
struct camss *camss;
|
||||
u8 id;
|
||||
|
|
@ -55,6 +69,7 @@ struct csiphy_device {
|
|||
u32 timer_clk_rate;
|
||||
struct csiphy_config cfg;
|
||||
struct v4l2_mbus_framefmt fmt[MSM_CSIPHY_PADS_NUM];
|
||||
const struct csiphy_hw_ops *ops;
|
||||
};
|
||||
|
||||
struct resources;
|
||||
|
|
@ -68,4 +83,6 @@ int msm_csiphy_register_entity(struct csiphy_device *csiphy,
|
|||
|
||||
void msm_csiphy_unregister_entity(struct csiphy_device *csiphy);
|
||||
|
||||
extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0;
|
||||
|
||||
#endif /* QC_MSM_CAMSS_CSIPHY_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue