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This round has a diffstat dominated by Qualcomm clk drivers. Honestly though 

that's just a bunch of data so the diffstat reflects that. Looking beyond that
 there's just a bunch of updates all around in various clk drivers. Renesas and
 NXP (for i.MX) are two SoC vendors that have a lot of patches in here. Overall
 the driver changes look to be mostly enabling more clks and non-critical fixes
 that we could hold until the next merge window.
 
 I'm especially excited about the series from Arnd that graduates clkdev to be
 the only implementation of clk_get() and clk_put(). That's a good step in the
 right direction to migreate eveerything over to the common clk framework. Now
 we don't have to worry about clkdev specific details, they're just part of the
 clk API now.
 
 Core:
  - clkdev is now the only option, i.e. clk_get()/clk_put() is implemented in
    only one place in the kernel instead of in drivers/clk/clkdev.c and in
    architectures that want their own implementation
 
 New Drivers:
  - Texas Instruments' LMK04832 Ultra Low-Noise JESD204B Compliant Clock
    Jitter Cleaner With Dual Loop PLLs
  - Qualcomm MDM9607 GCC
  - Qualcomm SC8180X display clks
  - Qualcomm SM6125 GCC
  - Qualcomm SM8250 CAMCC (camera)
  - Renesas RZ/G2L SoC
  - Hisilicon hi3559A SoC
 
 Updates:
  - Stop using clock-output-names in ST clk drivers (yay!)
  - Support secure mode of STM32MP1 SoCs
  - Improve clock support for Actions S500 SoC
  - duty cycle setting support on qcom clks
  - Add TI am33xx spread spectrum clock support
  - Use determine_rate() for the Amlogic pll ops instead of round_rate()
  - Restrict Amlogic gp0/1 and audio plls range on g12a/sm1
  - Improve Amlogic axg-audio controller error on deferral
  - Add NNA clocks on Amlogic g12a
  - Reduce memory footprint of Rockchip PLL rate tables
  - A fix for the newly added Rockchip rk3568 clk driver
  - Exported clock for the newly added Rockchip video decoder
  - Remove audio ipg clock from i.MX8MP
  - Remove deprecated legacy clock binding for i.MX SCU clock driver
  - Use common clk-imx8qxp for both i.MX8QXP and i.MX8QM
  - Add multiple clocks to clk-imx8qxp driver (enet, hdmi, lcdif, audio,
    parallel interface)
  - Add dedicated clock ops for i.MX paralel interface
  - Different fixes for clocks controlled by ATF on i.MX SoCs
  - Add A53/A72 frequency scaling support i.MX clk-scu driver
  - Add special case for DCSS clock on suspend for i.MX clk-scu driver
  - Add parent save/restore on suspend/resume to i.MX clk-scu driver
  - Skip runtime PM enablement for CPU clocks in i.MX clk-scu driver
  - Remove the sys1_pll/sys2_pll clock gates for i.MX8MQ and their
    bindings
  - Tegra clk driver no longer deasserts resets on clk_enable as it
    gets in the way of certain power-up sequences
  - Fix compile testing for Tegra clk driver
  - One patch to fix a divider on the Allwinner v3s Audio PLL
  - Add support for CPU core clock boost modes on Renesas R-Car Gen3
  - Add ISPCS (Image Signal Processor) clocks on Renesas R-Car V3U
  - Switch SH/R-Mobile and R-Car "DIV6" clocks to .determine_rate()
    and improve support for multiple parents
  - Switch Renesas RZ/N1 divider clocks to .determine_rate()
  - Add ZA2 (Audio Clock Generator) clock on Renesas R-Car D3
  - Convert ar7 to common clk framework
  - Convert ralink to common clk framework
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmDbu3sRHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSV+OA/9EEV3uuauFsxVm8ySX4T8amHAzE98asEX
 XldxMqBuGNnlqJn3A3LeGISKKafaRMkL/7xqBnTi9ZycDy1WRi2SiAKLTDoJCmi7
 ES32EBCO1O9D5uo4mYFsYgHUaxFmE+4tQbtDCttVt59yZEiiNPz0Lm8tWz5yuDzX
 IwCN8HrNShyL4dykTRUDuUkqrTg9sSqSvdG+XcyI24pgLtBWvJU32wIFfLN+/n9C
 JSyYwzHkajoeuv5kpAJ1IV/tzZgy77xQHunsatJWz1qJ1J2eFADWI2p3NVf88N21
 5Mw5xvikMJZ5Xq8pdZKiyEQOFfcxN/+k7hfc6eq3SDpbkaHPti9CX2rv9Uck6rdh
 Bigixsx9IHbQ+1CJAXZxcAJma/GwzoWW1irqzTQoChYgwlJIyPijFqbuJxqS4P0d
 9sEp0WvbdAEgnktiqs7gphki7Q04y2gUD3LKD6hz5sL0vZ+Dy1DY6olkWJefGrHo
 FDnEGf6gsP3vvvlJt5G2zeZQ/NzMKkfaIGLj/1hTtoLMaxpg282cmPXVUxD+ripW
 /GG/z14RdaHQXeMXduo+MeK5qUsO6LspnYown54IWilOOo1m/rfbun3yAFJaphG1
 ZQB+JDfeH8Cv6AYbNwbEpXyXyj2Rz5fGQjA31+97fCCxykZ+suBQkWqK/lUCmTyf
 ofwokRnKiYY=
 =YnCF
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This round has a diffstat dominated by Qualcomm clk drivers. Honestly
  though that's just a bunch of data so the diffstat reflects that.
  Looking beyond that there's just a bunch of updates all around in
  various clk drivers. Renesas and NXP (for i.MX) are two SoC vendors
  that have a lot of patches in here.

  Overall the driver changes look to be mostly enabling more clks and
  non-critical fixes that we could hold until the next merge window.

  I'm especially excited about the series from Arnd that graduates
  clkdev to be the only implementation of clk_get() and clk_put().
  That's a good step in the right direction to migreate eveerything over
  to the common clk framework. Now we don't have to worry about clkdev
  specific details, they're just part of the clk API now.

  Core:
   - clkdev is now the only option, i.e. clk_get()/clk_put() is
     implemented in only one place in the kernel instead of in
     drivers/clk/clkdev.c and in architectures that want their own
     implementation

  New Drivers:
   - Texas Instruments' LMK04832 Ultra Low-Noise JESD204B Compliant
     Clock Jitter Cleaner With Dual Loop PLLs
   - Qualcomm MDM9607 GCC
   - Qualcomm SC8180X display clks
   - Qualcomm SM6125 GCC
   - Qualcomm SM8250 CAMCC (camera)
   - Renesas RZ/G2L SoC
   - Hisilicon hi3559A SoC

  Updates:
   - Stop using clock-output-names in ST clk drivers (yay!)
   - Support secure mode of STM32MP1 SoCs
   - Improve clock support for Actions S500 SoC
   - duty cycle setting support on qcom clks
   - Add TI am33xx spread spectrum clock support
   - Use determine_rate() for the Amlogic pll ops instead of
     round_rate()
   - Restrict Amlogic gp0/1 and audio plls range on g12a/sm1
   - Improve Amlogic axg-audio controller error on deferral
   - Add NNA clocks on Amlogic g12a
   - Reduce memory footprint of Rockchip PLL rate tables
   - A fix for the newly added Rockchip rk3568 clk driver
   - Exported clock for the newly added Rockchip video decoder
   - Remove audio ipg clock from i.MX8MP
   - Remove deprecated legacy clock binding for i.MX SCU clock driver
   - Use common clk-imx8qxp for both i.MX8QXP and i.MX8QM
   - Add multiple clocks to clk-imx8qxp driver (enet, hdmi, lcdif,
     audio, parallel interface)
   - Add dedicated clock ops for i.MX paralel interface
   - Different fixes for clocks controlled by ATF on i.MX SoCs
   - Add A53/A72 frequency scaling support i.MX clk-scu driver
   - Add special case for DCSS clock on suspend for i.MX clk-scu driver
   - Add parent save/restore on suspend/resume to i.MX clk-scu driver
   - Skip runtime PM enablement for CPU clocks in i.MX clk-scu driver
   - Remove the sys1_pll/sys2_pll clock gates for i.MX8MQ and their
     bindings
   - Tegra clk driver no longer deasserts resets on clk_enable as it
     gets in the way of certain power-up sequences
   - Fix compile testing for Tegra clk driver
   - One patch to fix a divider on the Allwinner v3s Audio PLL
   - Add support for CPU core clock boost modes on Renesas R-Car Gen3
   - Add ISPCS (Image Signal Processor) clocks on Renesas R-Car V3U
   - Switch SH/R-Mobile and R-Car "DIV6" clocks to .determine_rate() and
     improve support for multiple parents
   - Switch Renesas RZ/N1 divider clocks to .determine_rate()
   - Add ZA2 (Audio Clock Generator) clock on Renesas R-Car D3
   - Convert ar7 to common clk framework
   - Convert ralink to common clk framework"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (161 commits)
  clk: zynqmp: Handle divider specific read only flag
  clk: zynqmp: Use firmware specific mux clock flags
  clk: zynqmp: Use firmware specific divider clock flags
  clk: zynqmp: Use firmware specific common clock flags
  clk: lmk04832: Use of match table
  clk: lmk04832: Depend on SPI
  clk: stm32mp1: new compatible for secure RCC support
  dt-bindings: clock: stm32mp1 new compatible for secure rcc
  dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15
  dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15
  dt-bindings: clock: add IDs for SCMI clocks on stm32mp15
  reset: stm32mp1: remove stm32mp1 reset
  clk: hisilicon: Add clock driver for hi3559A SoC
  dt-bindings: Document the hi3559a clock bindings
  clk: si5341: Add sysfs properties to allow checking/resetting device faults
  clk: si5341: Add silabs,iovdd-33 property
  clk: si5341: Add silabs,xaxb-ext-clk property
  clk: si5341: Allow different output VDD_SEL values
  clk: si5341: Update initialization magic
  clk: si5341: Check for input clock presence and PLL lock on startup
  ...
This commit is contained in:
Linus Torvalds 2021-07-01 13:26:16 -07:00
parent e058a84bfd d2b21013bf
commit 514798d365
163 changed files with 18185 additions and 2062 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
View File

@ -86,13 +86,11 @@ This binding uses the common clock binding[1].
Required properties:
- compatible: Should be one of:
"fsl,imx8qm-clock"
"fsl,imx8qxp-clock"
"fsl,imx8qm-clk"
"fsl,imx8qxp-clk"
followed by "fsl,scu-clk"
- #clock-cells: Should be either
2: Contains the Resource and Clock ID value.
or
1: Contains the Clock ID value. (DEPRECATED)
- #clock-cells: Should be 2.
Contains the Resource and Clock ID value.
- clocks: List of clock specifiers, must contain an entry for
each required entry in clock-names
- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"

19
Documentation/devicetree/bindings/clock/gpio-mux-clock.txt
View File

@ -1,19 +0,0 @@
Binding for simple gpio clock multiplexer.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "gpio-mux-clock".
- clocks: list of two references to parent clocks.
- #clock-cells : from common clock binding; shall be set to 0.
- select-gpios : GPIO reference for selecting the parent clock.
Example:
clock {
compatible = "gpio-mux-clock";
clocks = <&parentclk1>, <&parentclk2>;
#clock-cells = <0>;
select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
};

45
Documentation/devicetree/bindings/clock/gpio-mux-clock.yaml Normal file
View File

@ -0,0 +1,45 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/gpio-mux-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Simple GPIO clock multiplexer
maintainers:
- Sergej Sawazki <ce3a@gmx.de>
properties:
compatible:
const: gpio-mux-clock
clocks:
items:
- description: First parent clock
- description: Second parent clock
'#clock-cells':
const: 0
select-gpios:
description: GPIO reference for selecting the parent clock.
maxItems: 1
required:
- compatible
- clocks
- '#clock-cells'
- select-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
clock {
compatible = "gpio-mux-clock";
clocks = <&parentclk1>, <&parentclk2>;
#clock-cells = <0>;
select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
};

59
Documentation/devicetree/bindings/clock/hisilicon,hi3559av100-clock.yaml Normal file
View File

@ -0,0 +1,59 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/hisilicon,hi3559av100-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon SOC Clock for HI3559AV100
maintainers:
- Dongjiu Geng <gengdongjiu@huawei.com>
description: |
Hisilicon SOC clock control module which supports the clocks, resets and
power domains on HI3559AV100.
See also:
dt-bindings/clock/hi3559av100-clock.h
properties:
compatible:
enum:
- hisilicon,hi3559av100-clock
- hisilicon,hi3559av100-shub-clock
reg:
minItems: 1
maxItems: 2
'#clock-cells':
const: 1
'#reset-cells':
const: 2
description: |
First cell is reset request register offset.
Second cell is bit offset in reset request register.
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@12010000 {
compatible = "hisilicon,hi3559av100-clock";
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0x0 0x12010000 0x0 0x10000>;
};
};
...

4
Documentation/devicetree/bindings/clock/ingenic,cgu.yaml
View File

@ -22,6 +22,8 @@ select:
enum:
- ingenic,jz4740-cgu
- ingenic,jz4725b-cgu
- ingenic,jz4760-cgu
- ingenic,jz4760b-cgu
- ingenic,jz4770-cgu
- ingenic,jz4780-cgu
- ingenic,x1000-cgu
@ -49,6 +51,8 @@ properties:
- enum:
- ingenic,jz4740-cgu
- ingenic,jz4725b-cgu
- ingenic,jz4760-cgu
- ingenic,jz4760b-cgu
- ingenic,jz4770-cgu
- ingenic,jz4780-cgu
- ingenic,x1000-cgu

68
Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml Normal file
View File

@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,camcc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SM8250
maintainers:
- Jonathan Marek <jonathan@marek.ca>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
power domains on SM8250.
See also dt-bindings/clock/qcom,camcc-sm8250.h
properties:
compatible:
const: qcom,sm8250-camcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
clock-names:
items:
- const: bi_tcxo
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@ad00000 {
compatible = "qcom,sm8250-camcc";
reg = <0x0ad00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

1
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
View File

@ -20,6 +20,7 @@ description: |
properties:
compatible:
enum:
- qcom,sc8180x-dispcc
- qcom,sm8150-dispcc
- qcom,sm8250-dispcc

72
Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml Normal file
View File

@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM6125
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM6125.
See also:
- dt-bindings/clock/qcom,gcc-sm6125.h
properties:
compatible:
const: qcom,gcc-sm6125
clocks:
items:
- description: Board XO source
- description: Sleep clock source
clock-names:
items:
- const: bi_tcxo
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
clock-controller@1400000 {
compatible = "qcom,gcc-sm6125";
reg = <0x01400000 0x1f0000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "bi_tcxo", "sleep_clk";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
};
...

7
Documentation/devicetree/bindings/clock/qcom,gcc.yaml
View File

@ -26,9 +26,10 @@ description: |
- dt-bindings/reset/qcom,gcc-msm8939.h
- dt-bindings/clock/qcom,gcc-msm8660.h
- dt-bindings/reset/qcom,gcc-msm8660.h
- dt-bindings/clock/qcom,gcc-msm8974.h
- dt-bindings/reset/qcom,gcc-msm8974.h
- dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- dt-bindings/clock/qcom,gcc-msm8994.h
- dt-bindings/clock/qcom,gcc-mdm9607.h
- dt-bindings/clock/qcom,gcc-mdm9615.h
- dt-bindings/reset/qcom,gcc-mdm9615.h
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
@ -40,6 +41,8 @@ properties:
- qcom,gcc-ipq4019
- qcom,gcc-ipq6018
- qcom,gcc-ipq8064
- qcom,gcc-mdm9607
- qcom,gcc-msm8226
- qcom,gcc-msm8660
- qcom,gcc-msm8916
- qcom,gcc-msm8939

1
Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
View File

@ -12,6 +12,7 @@ Required properties :
"qcom,rpmcc-msm8660", "qcom,rpmcc"
"qcom,rpmcc-apq8060", "qcom,rpmcc"
"qcom,rpmcc-msm8226", "qcom,rpmcc"
"qcom,rpmcc-msm8916", "qcom,rpmcc"
"qcom,rpmcc-msm8936", "qcom,rpmcc"
"qcom,rpmcc-msm8974", "qcom,rpmcc"

83
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml Normal file
View File

@ -0,0 +1,83 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description: |
On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module
Standby Mode share the same register block.
They provide the following functionalities:
- The CPG block generates various core clocks,
- The Module Standby Mode block provides two functions:
1. Module Standby, providing a Clock Domain to control the clock supply
to individual SoC devices,
2. Reset Control, to perform a software reset of individual SoC devices.
properties:
compatible:
const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
description:
Clock source to CPG can be either from external clock input (EXCLK) or
crystal oscillator (XIN/XOUT).
const: extal
'#clock-cells':
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
<dt-bindings/clock/r9a07g044-cpg.h>
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.
const: 2
'#power-domain-cells':
description:
SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
can be power-managed through Module Standby should refer to the CPG device
node in their "power-domains" property, as documented by the generic PM
Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
const: 0
'#reset-cells':
description:
The single reset specifier cell must be the module number, as defined in
the <dt-bindings/clock/r9a07g044-cpg.h>.
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#power-domain-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g044-cpg";
reg = <0x11010000 0x10000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};

16
Documentation/devicetree/bindings/clock/silabs,si5341.txt
View File

@ -24,9 +24,8 @@ it.
The device type, speed grade and revision are determined runtime by probing.
The driver currently only supports XTAL input mode, and does not support any
fancy input configurations. They can still be programmed into the chip and
the driver will leave them "as is".
The driver currently does not support any fancy input configurations. They can
still be programmed into the chip and the driver will leave them "as is".
==I2C device node==
@ -45,9 +44,9 @@ Required properties:
corresponding to inputs. Use a fixed clock for the "xtal" input.
At least one must be present.
- clock-names: One of: "xtal", "in0", "in1", "in2"
- vdd-supply: Regulator node for VDD
Optional properties:
- vdd-supply: Regulator node for VDD
- vdda-supply: Regulator node for VDDA
- vdds-supply: Regulator node for VDDS
- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
@ -60,7 +59,14 @@ Optional properties:
be initialized, and always performs the soft-reset routine. Since this will
temporarily stop all output clocks, don't do this if the chip is generating
the CPU clock for example.
- silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used
in EXTCLK (external reference clock) rather than XTAL (crystal) mode.
- interrupts: Interrupt for INTRb pin.
- silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V
rather than 1.8V thresholds.
- vddoX-supply (where X is an output index): Regulator node for VDDO for the
specified output. The driver selects the output VDD_SEL setting based on this
voltage.
- #address-cells: shall be set to 1.
- #size-cells: shall be set to 0.
@ -77,8 +83,6 @@ Required child node properties:
- reg: number of clock output.
Optional child node properties:
- vdd-supply: Regulator node for VDD for this output. The driver selects default
values for common-mode and amplitude based on the voltage.
- silabs,format: Output format, one of:
1 = differential (defaults to LVDS levels)
2 = low-power (defaults to HCSL levels)

6
Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
View File

@ -54,7 +54,9 @@ properties:
compatible:
items:
- const: st,stm32mp1-rcc
- enum:
- st,stm32mp1-rcc-secure
- st,stm32mp1-rcc
- const: syscon
reg:
@ -71,7 +73,7 @@ additionalProperties: false
examples:
- |
rcc: rcc@50000000 {
compatible = "st,stm32mp1-rcc", "syscon";
compatible = "st,stm32mp1-rcc-secure", "syscon";
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;

3
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
View File

@ -10,7 +10,10 @@ Required properties:
- compatible : shall be:
"st,clkgen-pll0"
"st,clkgen-pll0-a0"
"st,clkgen-pll0-c0"
"st,clkgen-pll1"
"st,clkgen-pll1-c0"
"st,stih407-clkgen-plla9"
"st,stih418-clkgen-plla9"

10
Documentation/devicetree/bindings/clock/st/st,flexgen.txt
View File

@ -64,6 +64,16 @@ Required properties:
audio use case)
"st,flexgen-video", "st,flexgen" (enable clock propagation on parent
and activate synchronous mode)
"st,flexgen-stih407-a0"
"st,flexgen-stih410-a0"
"st,flexgen-stih407-c0"
"st,flexgen-stih410-c0"
"st,flexgen-stih418-c0"
"st,flexgen-stih407-d0"
"st,flexgen-stih410-d0"
"st,flexgen-stih407-d2"
"st,flexgen-stih418-d2"
"st,flexgen-stih407-d3"
- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
outputs).

3
Documentation/devicetree/bindings/clock/st/st,quadfs.txt
View File

@ -12,6 +12,9 @@ This binding uses the common clock binding[1].
Required properties:
- compatible : shall be:
"st,quadfs"
"st,quadfs-d0"
"st,quadfs-d2"
"st,quadfs-d3"
"st,quadfs-pll"

4
Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml
View File

@ -12,7 +12,9 @@ maintainers:
properties:
compatible:
items:
- const: ti,am654-ehrpwm-tbclk
- enum:
- ti,am654-ehrpwm-tbclk
- ti,am64-epwm-tbclk
- const: syscon
"#clock-cells":

209
Documentation/devicetree/bindings/clock/ti,lmk04832.yaml Normal file
View File

@ -0,0 +1,209 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ti,lmk04832.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for the Texas Instruments LMK04832
maintainers:
- Liam Beguin <liambeguin@gmail.com>
description: |
Devicetree binding for the LMK04832, a clock conditioner with JEDEC JESD204B
support. The LMK04832 is pin compatible with the LMK0482x family.
Link to datasheet, https://www.ti.com/lit/ds/symlink/lmk04832.pdf
properties:
compatible:
enum:
- ti,lmk04832
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
'#clock-cells':
const: 1
spi-max-frequency:
maximum: 5000000
clocks:
items:
- description: PLL2 reference clock.
clock-names:
items:
- const: oscin
reset-gpios:
maxItems: 1
ti,spi-4wire-rdbk:
description: |
Select SPI 4wire readback pin configuration.
Available readback pins are,
CLKin_SEL0 0
CLKin_SEL1 1
RESET 2
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
default: 1
ti,vco-hz:
description: Optional to set VCO frequency of the PLL in Hertz.
ti,sysref-ddly:
description: SYSREF digital delay value.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 8
maximum: 8191
default: 8
ti,sysref-mux:
description: |
SYSREF Mux configuration.
Available options are,
Normal SYNC 0
Re-clocked 1
SYSREF Pulser 2
SYSREF Continuous 3
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 3
ti,sync-mode:
description: SYNC pin configuration.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
default: 1
ti,sysref-pulse-count:
description:
Number of SYSREF pulses to send when SYSREF is not in continuous mode.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 4, 8]
default: 4
patternProperties:
"@[0-9a-d]+$":
type: object
description:
Child nodes used to configure output clocks.
properties:
reg:
description:
clock output identifier.
minimum: 0
maximum: 13
ti,clkout-fmt:
description:
Clock output format.
Available options are,
Powerdown 0x00
LVDS 0x01
HSDS 6 mA 0x02
HSDS 8 mA 0x03
LVPECL 1600 mV 0x04
LVPECL 2000 mV 0x05
LCPECL 0x06
CML 16 mA 0x07
CML 24 mA 0x08
CML 32 mA 0x09
CMOS (Off/Inverted) 0x0a
CMOS (Normal/Off) 0x0b
CMOS (Inverted/Inverted) 0x0c
CMOS (Inverted/Normal) 0x0d
CMOS (Normal/Inverted) 0x0e
CMOS (Normal/Normal) 0x0f
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 15
ti,clkout-sysref:
description:
Select SYSREF clock path for output clock.
type: boolean
required:
- reg
additionalProperties: false
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
clocks {
lmk04832_oscin: oscin {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <122880000>;
clock-output-names = "lmk04832-oscin";
};
};
spi0 {
#address-cells = <1>;
#size-cells = <0>;
lmk04832: clock-controller@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
compatible = "ti,lmk04832";
spi-max-frequency = <781250>;
reset-gpios = <&gpio_lmk 0 0 0>;
#clock-cells = <1>;
clocks = <&lmk04832_oscin>;
clock-names = "oscin";
ti,spi-4wire-rdbk = <0>;
ti,vco-hz = <2457600000>;
assigned-clocks =
<&lmk04832 0>, <&lmk04832 1>,
<&lmk04832 2>, <&lmk04832 3>,
<&lmk04832 4>,
<&lmk04832 6>, <&lmk04832 7>,
<&lmk04832 10>, <&lmk04832 11>;
assigned-clock-rates =
<122880000>, <384000>,
<122880000>, <384000>,
<122880000>,
<153600000>, <384000>,
<614400000>, <384000>;
clkout0@0 {
reg = <0>;
ti,clkout-fmt = <0x01>; // LVDS
};
clkout1@1 {
reg = <1>;
ti,clkout-fmt = <0x01>; // LVDS
ti,clkout-sysref;
};
};
};

20
Documentation/devicetree/bindings/clock/ti/dpll.txt
View File

@ -42,6 +42,11 @@ Required properties:
"idlest" - contains the idle status register base address
"mult-div1" - contains the multiplier / divider register base address
"autoidle" - contains the autoidle register base address (optional)
"ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
the frequency spreading register base address (optional)
"ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
the modulation frequency register base address
(optional)
ti,am3-* dpll types do not have autoidle register
ti,omap2-* dpll type does not support idlest / autoidle registers
@ -51,6 +56,14 @@ Optional properties:
- ti,low-power-stop : DPLL supports low power stop mode, gating output
- ti,low-power-bypass : DPLL output matches rate of parent bypass clock
- ti,lock : DPLL locks in programmed rate
- ti,min-div : the minimum divisor to start from to round the DPLL
target rate
- ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
spreading in permille (10th of a percent)
- ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
spectrum modulation frequency
- ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
to enable the downspread feature
Examples:
dpll_core_ck: dpll_core_ck@44e00490 {
@ -83,3 +96,10 @@ Examples:
clocks = <&sys_ck>, <&sys_ck>;
reg = <0x0500>, <0x0540>;
};
dpll_disp_ck: dpll_disp_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
};

2
arch/arm/Kconfig
View File

@ -353,7 +353,6 @@ config ARCH_EP93XX
select ARM_VIC
select GENERIC_IRQ_MULTI_HANDLER
select AUTO_ZRELADDR
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CPU_ARM920T
select GPIOLIB
@ -504,7 +503,6 @@ config ARCH_OMAP1
bool "TI OMAP1"
depends on MMU
select ARCH_OMAP
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select GENERIC_IRQ_MULTI_HANDLER

10
arch/arm/boot/dts/am33xx-clocks.dtsi
View File

@ -164,7 +164,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0490>, <0x045c>, <0x0468>;
reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
@ -204,7 +204,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0488>, <0x0420>, <0x042c>;
reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
@ -220,7 +220,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0494>, <0x0434>, <0x0440>;
reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
@ -244,7 +244,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0498>, <0x0448>, <0x0454>;
reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
@ -261,7 +261,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x048c>, <0x0470>, <0x049c>;
reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
};
dpll_per_m2_ck: dpll_per_m2_ck@4ac {

12
arch/arm/boot/dts/am43xx-clocks.dtsi
View File

@ -204,7 +204,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2d20>, <0x2d24>, <0x2d2c>;
reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
@ -250,7 +250,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2d60>, <0x2d64>, <0x2d6c>;
reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
@ -276,7 +276,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2da0>, <0x2da4>, <0x2dac>;
reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
@ -294,7 +294,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2e20>, <0x2e24>, <0x2e2c>;
reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
@ -313,7 +313,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2de0>, <0x2de4>, <0x2dec>;
reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
};
dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
@ -557,7 +557,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2e60>, <0x2e64>, <0x2e6c>;
reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
};
dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {

21
arch/m68k/coldfire/clk.c
View File

@ -73,20 +73,6 @@ struct clk_ops clk_ops1 = {
#endif /* MCFPM_PPMCR1 */
#endif /* MCFPM_PPMCR0 */
struct clk *clk_get(struct device *dev, const char *id)
{
const char *clk_name = dev ? dev_name(dev) : id ? id : NULL;
struct clk *clk;
unsigned i;
for (i = 0; (clk = mcf_clks[i]) != NULL; ++i)
if (!strcmp(clk->name, clk_name))
return clk;
pr_warn("clk_get: didn't find clock %s\n", clk_name);
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
int clk_enable(struct clk *clk)
{
unsigned long flags;
@ -117,13 +103,6 @@ void clk_disable(struct clk *clk)
}
EXPORT_SYMBOL(clk_disable);
void clk_put(struct clk *clk)
{
if (clk->enabled != 0)
pr_warn("clk_put %s still enabled\n", clk->name);
}
EXPORT_SYMBOL(clk_put);
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk)

25
arch/m68k/coldfire/m5206.c
View File

@ -10,6 +10,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -23,21 +24,15 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfi2c0,
NULL
static struct clk_lookup m5206_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -66,6 +61,8 @@ void __init config_BSP(char *commandp, int size)
mcf_mapirq2imr(28, MCFINTC_EINT4);
mcf_mapirq2imr(31, MCFINTC_EINT7);
m5206_i2c_init();
clkdev_add_table(m5206_clk_lookup, ARRAY_SIZE(m5206_clk_lookup));
}
/***************************************************************************/

51
arch/m68k/coldfire/m520x.c
View File

@ -12,6 +12,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -48,31 +49,29 @@ DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
DEFINE_CLK(0, "sdram.0", 42, MCF_CLK);
struct clk *mcf_clks[] = {
&__clk_0_2, /* flexbus */
&__clk_0_12, /* fec.0 */
&__clk_0_17, /* edma */
&__clk_0_18, /* intc.0 */
&__clk_0_21, /* iack.0 */
&__clk_0_22, /* imx1-i2c.0 */
&__clk_0_23, /* mcfqspi.0 */
&__clk_0_24, /* mcfuart.0 */
&__clk_0_25, /* mcfuart.1 */
&__clk_0_26, /* mcfuart.2 */
&__clk_0_28, /* mcftmr.0 */
&__clk_0_29, /* mcftmr.1 */
&__clk_0_30, /* mcftmr.2 */
&__clk_0_31, /* mcftmr.3 */
&__clk_0_32, /* mcfpit.0 */
&__clk_0_33, /* mcfpit.1 */
&__clk_0_34, /* mcfeport.0 */
&__clk_0_35, /* mcfwdt.0 */
&__clk_0_36, /* pll.0 */
&__clk_0_40, /* sys.0 */
&__clk_0_41, /* gpio.0 */
&__clk_0_42, /* sdram.0 */
NULL,
static struct clk_lookup m520x_clk_lookup[] = {
CLKDEV_INIT(NULL, "flexbus", &__clk_0_2),
CLKDEV_INIT("fec.0", NULL, &__clk_0_12),
CLKDEV_INIT("edma", NULL, &__clk_0_17),
CLKDEV_INIT("intc.0", NULL, &__clk_0_18),
CLKDEV_INIT("iack.0", NULL, &__clk_0_21),
CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
CLKDEV_INIT("mcfqspi.0", NULL, &__clk_0_23),
CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24),
CLKDEV_INIT("mcfuart.1", NULL, &__clk_0_25),
CLKDEV_INIT("mcfuart.2", NULL, &__clk_0_26),
CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28),
CLKDEV_INIT("mcftmr.1", NULL, &__clk_0_29),
CLKDEV_INIT("mcftmr.2", NULL, &__clk_0_30),
CLKDEV_INIT("mcftmr.3", NULL, &__clk_0_31),
CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32),
CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33),
CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_34),
CLKDEV_INIT("mcfwdt.0", NULL, &__clk_0_35),
CLKDEV_INIT(NULL, "pll.0", &__clk_0_36),
CLKDEV_INIT(NULL, "sys.0", &__clk_0_40),
CLKDEV_INIT("gpio.0", NULL, &__clk_0_41),
CLKDEV_INIT("sdram.0", NULL, &__clk_0_42),
};
static struct clk * const enable_clks[] __initconst = {
@ -115,6 +114,8 @@ static void __init m520x_clk_init(void)
/* make sure these clocks are disabled */
for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
__clk_init_disabled(disable_clks[i]);
clkdev_add_table(m520x_clk_lookup, ARRAY_SIZE(m520x_clk_lookup));
}
/***************************************************************************/

40
arch/m68k/coldfire/m523x.c
View File

@ -13,6 +13,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -26,31 +27,20 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcfpit0,
&clk_mcfpit1,
&clk_mcfpit2,
&clk_mcfpit3,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfuart2,
&clk_mcfqspi0,
&clk_fec0,
&clk_mcfi2c0,
NULL
struct clk_lookup m523x_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("fec.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -100,6 +90,8 @@ void __init config_BSP(char *commandp, int size)
m523x_fec_init();
m523x_qspi_init();
m523x_i2c_init();
clkdev_add_table(m523x_clk_lookup, ARRAY_SIZE(m523x_clk_lookup));
}
/***************************************************************************/

31
arch/m68k/coldfire/m5249.c
View File

@ -9,6 +9,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -23,25 +24,17 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfqspi0,
&clk_mcfi2c0,
&clk_mcfi2c1,
NULL
struct clk_lookup m5249_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys),
};
/***************************************************************************/
@ -137,6 +130,8 @@ void __init config_BSP(char *commandp, int size)
#endif
m5249_qspi_init();
m5249_i2c_init();
clkdev_add_table(m5249_clk_lookup, ARRAY_SIZE(m5249_clk_lookup));
}
/***************************************************************************/

31
arch/m68k/coldfire/m525x.c
View File

@ -9,6 +9,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -23,25 +24,17 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfqspi0,
&clk_mcfi2c0,
&clk_mcfi2c1,
NULL
static struct clk_lookup m525x_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys),
};
/***************************************************************************/
@ -88,6 +81,8 @@ void __init config_BSP(char *commandp, int size)
m525x_qspi_init();
m525x_i2c_init();
clkdev_add_table(m525x_clk_lookup, ARRAY_SIZE(m525x_clk_lookup));
}
/***************************************************************************/

33
arch/m68k/coldfire/m5272.c
View File

@ -10,6 +10,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -34,27 +35,18 @@ unsigned char ledbank = 0xff;
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK);
DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcftmr2,
&clk_mcftmr3,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfqspi0,
&clk_fec0,
NULL
static struct clk_lookup m5272_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.2", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.3", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("fec.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -128,6 +120,7 @@ static int __init init_BSP(void)
{
m5272_uarts_init();
fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
clkdev_add_table(m5272_clk_lookup, ARRAY_SIZE(m5272_clk_lookup));
return 0;
}

42
arch/m68k/coldfire/m527x.c
View File

@ -13,6 +13,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -27,33 +28,21 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcfpit0,
&clk_mcfpit1,
&clk_mcfpit2,
&clk_mcfpit3,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfuart2,
&clk_mcfqspi0,
&clk_fec0,
&clk_fec1,
&clk_mcfi2c0,
NULL
static struct clk_lookup m527x_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("fec.0", NULL, &clk_sys),
CLKDEV_INIT("fec.1", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -151,6 +140,7 @@ void __init config_BSP(char *commandp, int size)
m527x_fec_init();
m527x_qspi_init();
m527x_i2c_init();
clkdev_add_table(m527x_clk_lookup, ARRAY_SIZE(m527x_clk_lookup));
}
/***************************************************************************/

40
arch/m68k/coldfire/m528x.c
View File

@ -13,6 +13,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -28,31 +29,20 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcfpit0,
&clk_mcfpit1,
&clk_mcfpit2,
&clk_mcfpit3,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfuart2,
&clk_mcfqspi0,
&clk_fec0,
&clk_mcfi2c0,
NULL
static struct clk_lookup m528x_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("fec.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -146,6 +136,8 @@ void __init config_BSP(char *commandp, int size)
m528x_fec_init();
m528x_qspi_init();
m528x_i2c_init();
clkdev_add_table(m528x_clk_lookup, ARRAY_SIZE(m528x_clk_lookup));
}
/***************************************************************************/

25
arch/m68k/coldfire/m5307.c
View File

@ -10,6 +10,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -32,21 +33,15 @@ unsigned char ledbank = 0xff;
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfi2c0,
NULL
static struct clk_lookup m5307_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -88,6 +83,8 @@ void __init config_BSP(char *commandp, int size)
wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
#endif
m5307_i2c_init();
clkdev_add_table(m5307_clk_lookup, ARRAY_SIZE(m5307_clk_lookup));
}
/***************************************************************************/

78
arch/m68k/coldfire/m53xx.c
View File

@ -13,6 +13,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -65,45 +66,42 @@ DEFINE_CLK(1, "mdha.0", 32, MCF_CLK);
DEFINE_CLK(1, "skha.0", 33, MCF_CLK);
DEFINE_CLK(1, "rng.0", 34, MCF_CLK);
struct clk *mcf_clks[] = {
&__clk_0_2, /* flexbus */
&__clk_0_8, /* mcfcan.0 */
&__clk_0_12, /* fec.0 */
&__clk_0_17, /* edma */
&__clk_0_18, /* intc.0 */
&__clk_0_19, /* intc.1 */
&__clk_0_21, /* iack.0 */
&__clk_0_22, /* imx1-i2c.0 */
&__clk_0_23, /* mcfqspi.0 */
&__clk_0_24, /* mcfuart.0 */
&__clk_0_25, /* mcfuart.1 */
&__clk_0_26, /* mcfuart.2 */
&__clk_0_28, /* mcftmr.0 */
&__clk_0_29, /* mcftmr.1 */
&__clk_0_30, /* mcftmr.2 */
&__clk_0_31, /* mcftmr.3 */
&__clk_0_32, /* mcfpit.0 */
&__clk_0_33, /* mcfpit.1 */
&__clk_0_34, /* mcfpit.2 */
&__clk_0_35, /* mcfpit.3 */
&__clk_0_36, /* mcfpwm.0 */
&__clk_0_37, /* mcfeport.0 */
&__clk_0_38, /* mcfwdt.0 */
&__clk_0_40, /* sys.0 */
&__clk_0_41, /* gpio.0 */
&__clk_0_42, /* mcfrtc.0 */
&__clk_0_43, /* mcflcd.0 */
&__clk_0_44, /* mcfusb-otg.0 */
&__clk_0_45, /* mcfusb-host.0 */
&__clk_0_46, /* sdram.0 */
&__clk_0_47, /* ssi.0 */
&__clk_0_48, /* pll.0 */
&__clk_1_32, /* mdha.0 */
&__clk_1_33, /* skha.0 */
&__clk_1_34, /* rng.0 */
NULL,
static struct clk_lookup m53xx_clk_lookup[] = {
CLKDEV_INIT("flexbus", NULL, &__clk_0_2),
CLKDEV_INIT("mcfcan.0", NULL, &__clk_0_8),
CLKDEV_INIT("fec.0", NULL, &__clk_0_12),
CLKDEV_INIT("edma", NULL, &__clk_0_17),
CLKDEV_INIT("intc.0", NULL, &__clk_0_18),
CLKDEV_INIT("intc.1", NULL, &__clk_0_19),
CLKDEV_INIT("iack.0", NULL, &__clk_0_21),
CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
CLKDEV_INIT("mcfqspi.0", NULL, &__clk_0_23),
CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24),
CLKDEV_INIT("mcfuart.1", NULL, &__clk_0_25),
CLKDEV_INIT("mcfuart.2", NULL, &__clk_0_26),
CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28),
CLKDEV_INIT("mcftmr.1", NULL, &__clk_0_29),
CLKDEV_INIT("mcftmr.2", NULL, &__clk_0_30),
CLKDEV_INIT("mcftmr.3", NULL, &__clk_0_31),
CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32),
CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33),
CLKDEV_INIT("mcfpit.2", NULL, &__clk_0_34),
CLKDEV_INIT("mcfpit.3", NULL, &__clk_0_35),
CLKDEV_INIT("mcfpwm.0", NULL, &__clk_0_36),
CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_37),
CLKDEV_INIT("mcfwdt.0", NULL, &__clk_0_38),
CLKDEV_INIT(NULL, "sys.0", &__clk_0_40),
CLKDEV_INIT("gpio.0", NULL, &__clk_0_41),
CLKDEV_INIT("mcfrtc.0", NULL, &__clk_0_42),
CLKDEV_INIT("mcflcd.0", NULL, &__clk_0_43),
CLKDEV_INIT("mcfusb-otg.0", NULL, &__clk_0_44),
CLKDEV_INIT("mcfusb-host.0", NULL, &__clk_0_45),
CLKDEV_INIT("sdram.0", NULL, &__clk_0_46),
CLKDEV_INIT("ssi.0", NULL, &__clk_0_47),
CLKDEV_INIT(NULL, "pll.0", &__clk_0_48),
CLKDEV_INIT("mdha.0", NULL, &__clk_1_32),
CLKDEV_INIT("skha.0", NULL, &__clk_1_33),
CLKDEV_INIT("rng.0", NULL, &__clk_1_34),
};
static struct clk * const enable_clks[] __initconst = {
@ -158,6 +156,8 @@ static void __init m53xx_clk_init(void)
/* make sure these clocks are disabled */
for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
__clk_init_disabled(disable_clks[i]);
clkdev_add_table(m53xx_clk_lookup, ARRAY_SIZE(m53xx_clk_lookup));
}
/***************************************************************************/

25
arch/m68k/coldfire/m5407.c
View File

@ -10,6 +10,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -23,21 +24,15 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfi2c0,
NULL
static struct clk_lookup m5407_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -63,6 +58,8 @@ void __init config_BSP(char *commandp, int size)
mcf_mapirq2imr(29, MCFINTC_EINT5);
mcf_mapirq2imr(31, MCFINTC_EINT7);
m5407_i2c_init();
clkdev_add_table(m5407_clk_lookup, ARRAY_SIZE(m5407_clk_lookup));
}
/***************************************************************************/

126
arch/m68k/coldfire/m5441x.c
View File

@ -5,6 +5,7 @@
* (C) Copyright Steven King <sfking@fdwdc.com>
*/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -78,72 +79,67 @@ DEFINE_CLK(2, "ipg.0", 0, MCF_CLK);
DEFINE_CLK(2, "ahb.0", 1, MCF_CLK);
DEFINE_CLK(2, "per.0", 2, MCF_CLK);
struct clk *mcf_clks[] = {
&__clk_0_2,
&__clk_0_8,
&__clk_0_9,
&__clk_0_14,
&__clk_0_15,
&__clk_0_17,
&__clk_0_18,
&__clk_0_19,
&__clk_0_20,
&__clk_0_22,
&__clk_0_23,
&__clk_0_24,
&__clk_0_25,
&__clk_0_26,
&__clk_0_27,
&__clk_0_28,
&__clk_0_29,
&__clk_0_30,
&__clk_0_31,
&__clk_0_32,
&__clk_0_33,
&__clk_0_34,
&__clk_0_35,
&__clk_0_37,
&__clk_0_38,
&__clk_0_39,
&__clk_0_42,
&__clk_0_43,
&__clk_0_44,
&__clk_0_45,
&__clk_0_46,
&__clk_0_47,
&__clk_0_48,
&__clk_0_49,
&__clk_0_50,
&__clk_0_51,
&__clk_0_53,
&__clk_0_54,
&__clk_0_55,
&__clk_0_56,
&__clk_0_63,
&__clk_1_2,
&__clk_1_4,
&__clk_1_5,
&__clk_1_6,
&__clk_1_7,
&__clk_1_24,
&__clk_1_25,
&__clk_1_26,
&__clk_1_27,
&__clk_1_28,
&__clk_1_29,
&__clk_1_34,
&__clk_1_36,
&__clk_1_37,
&__clk_2_0,
&__clk_2_1,
&__clk_2_2,
NULL,
static struct clk_lookup m5411x_clk_lookup[] = {
CLKDEV_INIT("flexbus", NULL, &__clk_0_2),
CLKDEV_INIT("mcfcan.0", NULL, &__clk_0_8),
CLKDEV_INIT("mcfcan.1", NULL, &__clk_0_9),
CLKDEV_INIT("imx1-i2c.1", NULL, &__clk_0_14),
CLKDEV_INIT("mcfdspi.1", NULL, &__clk_0_15),
CLKDEV_INIT("edma", NULL, &__clk_0_17),
CLKDEV_INIT("intc.0", NULL, &__clk_0_18),
CLKDEV_INIT("intc.1", NULL, &__clk_0_19),
CLKDEV_INIT("intc.2", NULL, &__clk_0_20),
CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
CLKDEV_INIT("fsl-dspi.0", NULL, &__clk_0_23),
CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24),
CLKDEV_INIT("mcfuart.1", NULL, &__clk_0_25),
CLKDEV_INIT("mcfuart.2", NULL, &__clk_0_26),
CLKDEV_INIT("mcfuart.3", NULL, &__clk_0_27),
CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28),
CLKDEV_INIT("mcftmr.1", NULL, &__clk_0_29),
CLKDEV_INIT("mcftmr.2", NULL, &__clk_0_30),
CLKDEV_INIT("mcftmr.3", NULL, &__clk_0_31),
CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32),
CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33),
CLKDEV_INIT("mcfpit.2", NULL, &__clk_0_34),
CLKDEV_INIT("mcfpit.3", NULL, &__clk_0_35),
CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_37),
CLKDEV_INIT("mcfadc.0", NULL, &__clk_0_38),
CLKDEV_INIT("mcfdac.0", NULL, &__clk_0_39),
CLKDEV_INIT("mcfrtc.0", NULL, &__clk_0_42),
CLKDEV_INIT("mcfsim.0", NULL, &__clk_0_43),
CLKDEV_INIT("mcfusb-otg.0", NULL, &__clk_0_44),
CLKDEV_INIT("mcfusb-host.0", NULL, &__clk_0_45),
CLKDEV_INIT("mcfddr-sram.0", NULL, &__clk_0_46),
CLKDEV_INIT("mcfssi.0", NULL, &__clk_0_47),
CLKDEV_INIT(NULL, "pll.0", &__clk_0_48),
CLKDEV_INIT("mcfrng.0", NULL, &__clk_0_49),
CLKDEV_INIT("mcfssi.1", NULL, &__clk_0_50),
CLKDEV_INIT("sdhci-esdhc-mcf.0", NULL, &__clk_0_51),
CLKDEV_INIT("enet-fec.0", NULL, &__clk_0_53),
CLKDEV_INIT("enet-fec.1", NULL, &__clk_0_54),
CLKDEV_INIT("switch.0", NULL, &__clk_0_55),
CLKDEV_INIT("switch.1", NULL, &__clk_0_56),
CLKDEV_INIT("nand.0", NULL, &__clk_0_63),
CLKDEV_INIT("mcfow.0", NULL, &__clk_1_2),
CLKDEV_INIT("imx1-i2c.2", NULL, &__clk_1_4),
CLKDEV_INIT("imx1-i2c.3", NULL, &__clk_1_5),
CLKDEV_INIT("imx1-i2c.4", NULL, &__clk_1_6),
CLKDEV_INIT("imx1-i2c.5", NULL, &__clk_1_7),
CLKDEV_INIT("mcfuart.4", NULL, &__clk_1_24),
CLKDEV_INIT("mcfuart.5", NULL, &__clk_1_25),
CLKDEV_INIT("mcfuart.6", NULL, &__clk_1_26),
CLKDEV_INIT("mcfuart.7", NULL, &__clk_1_27),
CLKDEV_INIT("mcfuart.8", NULL, &__clk_1_28),
CLKDEV_INIT("mcfuart.9", NULL, &__clk_1_29),
CLKDEV_INIT("mcfpwm.0", NULL, &__clk_1_34),
CLKDEV_INIT(NULL, "sys.0", &__clk_1_36),
CLKDEV_INIT("gpio.0", NULL, &__clk_1_37),
CLKDEV_INIT("ipg.0", NULL, &__clk_2_0),
CLKDEV_INIT("ahb.0", NULL, &__clk_2_1),
CLKDEV_INIT("per.0", NULL, &__clk_2_2),
};
static struct clk * const enable_clks[] __initconst = {
/* make sure these clocks are enabled */
&__clk_0_15, /* dspi.1 */
@ -228,6 +224,8 @@ static void __init m5441x_clk_init(void)
/* make sure these clocks are disabled */
for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
__clk_init_disabled(disable_clks[i]);
clkdev_add_table(m5411x_clk_lookup, ARRAY_SIZE(m5411x_clk_lookup));
}
static void __init m5441x_uarts_init(void)

31
arch/m68k/coldfire/m54xx.c
View File

@ -9,6 +9,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -32,25 +33,17 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK);
DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcfslt0,
&clk_mcfslt1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfuart2,
&clk_mcfuart3,
&clk_mcfi2c0,
NULL
static struct clk_lookup m54xx_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcfslt.0", NULL, &clk_sys),
CLKDEV_INIT("mcfslt.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.3", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -100,6 +93,8 @@ void __init config_BSP(char *commandp, int size)
mach_sched_init = hw_timer_init;
m54xx_uarts_init();
m54xx_i2c_init();
clkdev_add_table(m54xx_clk_lookup, ARRAY_SIZE(m54xx_clk_lookup));
}
/***************************************************************************/

5
arch/m68k/include/asm/mcfclk.h
View File

@ -15,15 +15,12 @@ struct clk_ops {
};
struct clk {
const char *name;
struct clk_ops *clk_ops;
unsigned long rate;
unsigned long enabled;
u8 slot;
};
extern struct clk *mcf_clks[];
#ifdef MCFPM_PPMCR0
extern struct clk_ops clk_ops0;
#ifdef MCFPM_PPMCR1
@ -34,7 +31,6 @@ extern struct clk_ops clk_ops2;
#define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
static struct clk __clk_##clk_bank##_##clk_slot = { \
.name = clk_name, \
.clk_ops = &clk_ops##clk_bank, \
.rate = clk_rate, \
.slot = clk_slot, \
@ -45,7 +41,6 @@ void __clk_init_disabled(struct clk *);
#else
#define DEFINE_CLK(clk_ref, clk_name, clk_rate) \
static struct clk clk_##clk_ref = { \
.name = clk_name, \
.rate = clk_rate, \
}
#endif /* MCFPM_PPMCR0 */

6
arch/mips/Kconfig
View File

@ -201,6 +201,7 @@ config MIPS_ALCHEMY
config AR7
bool "Texas Instruments AR7"
select BOOT_ELF32
select COMMON_CLK
select DMA_NONCOHERENT
select CEVT_R4K
select CSRC_R4K
@ -215,7 +216,6 @@ config AR7
select SYS_SUPPORTS_ZBOOT_UART16550
select GPIOLIB
select VLYNQ
select HAVE_LEGACY_CLK
help
Support for the Texas Instruments AR7 System-on-a-Chip
family: TNETD7100, 7200 and 7300.
@ -332,7 +332,6 @@ config BCM63XX
select SWAP_IO_SPACE
select GPIOLIB
select MIPS_L1_CACHE_SHIFT_4
select CLKDEV_LOOKUP
select HAVE_LEGACY_CLK
help
Support for BCM63XX based boards
@ -446,7 +445,6 @@ config LANTIQ
select GPIOLIB
select SWAP_IO_SPACE
select BOOT_RAW
select CLKDEV_LOOKUP
select HAVE_LEGACY_CLK
select USE_OF
select PINCTRL
@ -630,6 +628,7 @@ config MACH_NINTENDO64
config RALINK
bool "Ralink based machines"
select CEVT_R4K
select COMMON_CLK
select CSRC_R4K
select BOOT_RAW
select DMA_NONCOHERENT
@ -642,7 +641,6 @@ config RALINK
select SYS_SUPPORTS_MIPS16
select SYS_SUPPORTS_ZBOOT
select SYS_HAS_EARLY_PRINTK
select CLKDEV_LOOKUP
select ARCH_HAS_RESET_CONTROLLER
select RESET_CONTROLLER

113
arch/mips/ar7/clock.c
View File

@ -13,7 +13,9 @@
#include <linux/gcd.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/clkdev.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <asm/addrspace.h>
#include <asm/mach-ar7/ar7.h>
@ -84,17 +86,17 @@ struct tnetd7200_clocks {
struct tnetd7200_clock usb;
};
static struct clk bus_clk = {
struct clk_rate {
u32 rate;
};
static struct clk_rate bus_clk = {
.rate = 125000000,
};
static struct clk cpu_clk = {
static struct clk_rate cpu_clk = {
.rate = 150000000,
};
static struct clk dsp_clk;
static struct clk vbus_clk;
static void approximate(int base, int target, int *prediv,
int *postdiv, int *mul)
{
@ -240,6 +242,8 @@ static void __init tnetd7300_init_clocks(void)
struct tnetd7300_clocks *clocks =
ioremap(UR8_REGS_CLOCKS,
sizeof(struct tnetd7300_clocks));
u32 dsp_clk;
struct clk *clk;
bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
&clocks->bus, bootcr, AR7_AFE_CLOCK);
@ -250,12 +254,18 @@ static void __init tnetd7300_init_clocks(void)
else
cpu_clk.rate = bus_clk.rate;
if (dsp_clk.rate == 250000000)
dsp_clk = tnetd7300_dsp_clock();
if (dsp_clk == 250000000)
tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
bootcr, dsp_clk.rate);
bootcr, dsp_clk);
iounmap(clocks);
iounmap(bootcr);
clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate);
clkdev_create(clk, "cpu", NULL);
clk = clk_register_fixed_rate(NULL, "dsp", NULL, 0, dsp_clk);
clkdev_create(clk, "dsp", NULL);
}
static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
@ -327,6 +337,7 @@ static void __init tnetd7200_init_clocks(void)
int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
int usb_base, usb_mul, usb_prediv, usb_postdiv;
struct clk *clk;
cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
@ -395,100 +406,34 @@ static void __init tnetd7200_init_clocks(void)
usb_prediv, usb_postdiv, -1, usb_mul,
TNETD7200_DEF_USB_CLK);
dsp_clk.rate = cpu_clk.rate;
iounmap(clocks);
iounmap(bootcr);
}
/*
* Linux clock API
*/
int clk_enable(struct clk *clk)
{
return 0;
clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate);
clkdev_create(clk, "cpu", NULL);
clkdev_create(clk, "dsp", NULL);
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk)
return 0;
return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);
struct clk *clk_get(struct device *dev, const char *id)
{
if (!strcmp(id, "bus"))
return &bus_clk;
/* cpmac and vbus share the same rate */
if (!strcmp(id, "cpmac"))
return &vbus_clk;
if (!strcmp(id, "cpu"))
return &cpu_clk;
if (!strcmp(id, "dsp"))
return &dsp_clk;
if (!strcmp(id, "vbus"))
return &vbus_clk;
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);
void __init ar7_init_clocks(void)
{
struct clk *clk;
switch (ar7_chip_id()) {
case AR7_CHIP_7100:
case AR7_CHIP_7200:
tnetd7200_init_clocks();
break;
case AR7_CHIP_7300:
dsp_clk.rate = tnetd7300_dsp_clock();
tnetd7300_init_clocks();
break;
default:
break;
}
clk = clk_register_fixed_rate(NULL, "bus", NULL, 0, bus_clk.rate);
clkdev_create(clk, "bus", NULL);
/* adjust vbus clock rate */
vbus_clk.rate = bus_clk.rate / 2;
clk = clk_register_fixed_factor(NULL, "vbus", "bus", 0, 1, 2);
clkdev_create(clk, "vbus", NULL);
clkdev_create(clk, "cpmac", "cpmac.1");
clkdev_create(clk, "cpmac", "cpmac.1");
}
/* dummy functions, should not be called */
long clk_round_rate(struct clk *clk, unsigned long rate)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_set_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
WARN_ON(clk);
return NULL;
}
EXPORT_SYMBOL(clk_get_parent);

4
arch/mips/include/asm/mach-ar7/ar7.h
View File

@ -131,10 +131,6 @@ static inline u8 ar7_chip_rev(void)
0x14))) >> 16) & 0xff;
}
struct clk {
unsigned int rate;
};
static inline int ar7_has_high_cpmac(void)
{
u16 chip_id = ar7_chip_id();

1
arch/mips/pic32/Kconfig
View File

@ -17,7 +17,6 @@ config PIC32MZDA
select SYS_SUPPORTS_LITTLE_ENDIAN
select GPIOLIB
select COMMON_CLK
select CLKDEV_LOOKUP
select LIBFDT
select USE_OF
select PINCTRL

5
arch/mips/ralink/Kconfig
View File

@ -28,22 +28,18 @@ choice
bool "RT288x"
select MIPS_AUTO_PFN_OFFSET
select MIPS_L1_CACHE_SHIFT_4
select HAVE_LEGACY_CLK
select HAVE_PCI
config SOC_RT305X
bool "RT305x"
select HAVE_LEGACY_CLK
config SOC_RT3883
bool "RT3883"
select HAVE_LEGACY_CLK
select HAVE_PCI
config SOC_MT7620
bool "MT7620/8"
select CPU_MIPSR2_IRQ_VI
select HAVE_LEGACY_CLK
select HAVE_PCI
config SOC_MT7621
@ -54,7 +50,6 @@ choice
select SYS_SUPPORTS_MIPS_CPS
select SYS_SUPPORTS_HIGHMEM
select MIPS_GIC
select COMMON_CLK
select CLKSRC_MIPS_GIC
select HAVE_PCI if PCI_MT7621
select SOC_BUS

64
arch/mips/ralink/clk.c
View File

@ -10,80 +10,22 @@
#include <linux/export.h>
#include <linux/clkdev.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <asm/time.h>
#include "common.h"
struct clk {
struct clk_lookup cl;
unsigned long rate;
};
void ralink_clk_add(const char *dev, unsigned long rate)
{
struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate);
if (!clk)
panic("failed to add clock");
clk->cl.dev_id = dev;
clk->cl.clk = clk;
clk->rate = rate;
clkdev_add(&clk->cl);
clkdev_create(clk, NULL, "%s", dev);
}
/*
* Linux clock API
*/
int clk_enable(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL_GPL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL_GPL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk)
return 0;
return clk->rate;
}
EXPORT_SYMBOL_GPL(clk_get_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
return -1;
}
EXPORT_SYMBOL_GPL(clk_set_rate);
long clk_round_rate(struct clk *clk, unsigned long rate)
{
return -1;
}
EXPORT_SYMBOL_GPL(clk_round_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
WARN_ON(clk);
return -1;
}
EXPORT_SYMBOL_GPL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
WARN_ON(clk);
return NULL;
}
EXPORT_SYMBOL_GPL(clk_get_parent);
void __init plat_time_init(void)
{
struct clk *clk;

1
arch/sh/Kconfig
View File

@ -14,7 +14,6 @@ config SUPERH
select ARCH_HIBERNATION_POSSIBLE if MMU
select ARCH_MIGHT_HAVE_PC_PARPORT
select ARCH_WANT_IPC_PARSE_VERSION
select CLKDEV_LOOKUP
select CPU_NO_EFFICIENT_FFS
select DMA_DECLARE_COHERENT
select GENERIC_ATOMIC64

30
drivers/clk/Kconfig
View File

@ -6,10 +6,6 @@ config HAVE_CLK
The <linux/clk.h> calls support software clock gating and
thus are a key power management tool on many systems.
config CLKDEV_LOOKUP
bool
select HAVE_CLK
config HAVE_CLK_PREPARE
bool
@ -26,7 +22,7 @@ menuconfig COMMON_CLK
bool "Common Clock Framework"
depends on !HAVE_LEGACY_CLK
select HAVE_CLK_PREPARE
select CLKDEV_LOOKUP
select HAVE_CLK
select SRCU
select RATIONAL
help
@ -55,6 +51,14 @@ config CLK_HSDK
This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
control.
config LMK04832
tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
depends on SPI
select REGMAP_SPI
help
Say yes here to build support for Texas Instruments' LMK04832 Ultra
Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
config COMMON_CLK_MAX77686
tristate "Clock driver for Maxim 77620/77686/77802 MFD"
depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
@ -335,6 +339,16 @@ config COMMON_CLK_STM32MP157
help
Support for stm32mp157 SoC family clocks
config COMMON_CLK_STM32MP157_SCMI
bool "stm32mp157 Clock driver with Trusted Firmware"
depends on COMMON_CLK_STM32MP157
select COMMON_CLK_SCMI
select ARM_SCMI_PROTOCOL
default y
help
Support for stm32mp157 SoC family clocks with Trusted Firmware using
SCMI protocol.
config COMMON_CLK_STM32F
def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
help
@ -358,10 +372,10 @@ config COMMON_CLK_MMP2_AUDIO
config COMMON_CLK_BD718XX
tristate "Clock driver for 32K clk gates on ROHM PMICs"
depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528 || MFD_ROHM_BD71828
depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828
help
This driver supports ROHM BD71837, ROHM BD71847, ROHM BD71828 and
ROHM BD70528 PMICs clock gates.
This driver supports ROHM BD71837, BD71847, BD71850, BD71815
and BD71828 PMICs clock gates.
config COMMON_CLK_FIXED_MMIO
bool "Clock driver for Memory Mapped Fixed values"

4
drivers/clk/Makefile
View File

@ -1,7 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
# common clock types
obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o
obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o clkdev.o
obj-$(CONFIG_COMMON_CLK) += clk.o
obj-$(CONFIG_COMMON_CLK) += clk-divider.o
obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
@ -37,6 +36,7 @@ obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o
obj-$(CONFIG_LMK04832) += clk-lmk04832.o
obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o

92
drivers/clk/actions/owl-s500.c
View File

@ -113,6 +113,7 @@ static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" };
static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" };
static const char * const pwm_clk_mux_p[] = { "losc", "hosc" };
static const char * const ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
static const char * const nic_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
static const char * const uart_clk_mux_p[] = { "hosc", "dev_pll_clk" };
static const char * const de_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
static const char * const i2s_clk_mux_p[] = { "audio_pll_clk" };
@ -127,8 +128,7 @@ static struct clk_factor_table sd_factor_table[] = {
{ 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
{ 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
{ 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
{ 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 },
{ 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 },
{ 24, 1, 25 },
/* bit8: /128 */
{ 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
@ -137,19 +137,20 @@ static struct clk_factor_table sd_factor_table[] = {
{ 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
{ 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
{ 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
{ 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 },
{ 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 },
{ 280, 1, 25 * 128 },
{ 0, 0, 0 },
};
static struct clk_factor_table bisp_factor_table[] = {
{ 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
{ 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
static struct clk_factor_table de_factor_table[] = {
{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
{ 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
{ 8, 1, 12 },
{ 0, 0, 0 },
};
static struct clk_factor_table ahb_factor_table[] = {
{ 1, 1, 2 }, { 2, 1, 3 },
static struct clk_factor_table hde_factor_table[] = {
{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
{ 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
{ 0, 0, 0 },
};
@ -158,6 +159,13 @@ static struct clk_div_table rmii_ref_div_table[] = {
{ 0, 0 },
};
static struct clk_div_table std12rate_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
{ 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
{ 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
{ 0, 0 },
};
static struct clk_div_table i2s_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
{ 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
@ -174,7 +182,6 @@ static struct clk_div_table nand_div_table[] = {
/* mux clock */
static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
/* gate clocks */
static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
@ -187,45 +194,60 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
/* divider clocks */
static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
static OWL_DIVIDER(apb_clk, "apb_clk", "nic_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
/* factor clocks */
static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0);
static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0);
static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0);
static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0);
static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0);
/* composite clocks */
static OWL_COMP_DIV(nic_clk, "nic_clk", nic_clk_mux_p,
OWL_MUX_HW(CMU_BUSCLK1, 4, 3),
{ 0 },
OWL_DIVIDER_HW(CMU_BUSCLK1, 16, 2, 0, NULL),
0);
static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p,
OWL_MUX_HW(CMU_BUSCLK1, 8, 3),
{ 0 },
OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
CLK_SET_RATE_PARENT);
static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk",
{ 0 },
1, 1, 0);
static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
OWL_MUX_HW(CMU_VCECLK, 4, 2),
OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table),
OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
0);
static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
OWL_MUX_HW(CMU_VDECLK, 4, 2),
OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table),
OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
0);
static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p,
static OWL_COMP_DIV(bisp_clk, "bisp_clk", bisp_clk_mux_p,
OWL_MUX_HW(CMU_BISPCLK, 4, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table),
OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table),
0);
static OWL_COMP_FACTOR(sensor0_clk, "sensor0_clk", sensor_clk_mux_p,
static OWL_COMP_DIV(sensor0_clk, "sensor0_clk", sensor_clk_mux_p,
OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
OWL_FACTOR_HW(CMU_SENSORCLK, 0, 3, 0, bisp_factor_table),
CLK_IGNORE_UNUSED);
OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table),
0);
static OWL_COMP_FACTOR(sensor1_clk, "sensor1_clk", sensor_clk_mux_p,
static OWL_COMP_DIV(sensor1_clk, "sensor1_clk", sensor_clk_mux_p,
OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
OWL_FACTOR_HW(CMU_SENSORCLK, 8, 3, 0, bisp_factor_table),
CLK_IGNORE_UNUSED);
OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table),
0);
static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
OWL_MUX_HW(CMU_SD0CLK, 9, 1),
@ -302,10 +324,14 @@ static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk",
OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
1, 5, 0);
static OWL_COMP_FIXED_FACTOR(ethernet_clk, "ethernet_clk", "ethernet_pll_clk",
OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0),
1, 20, 0);
static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART0CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
@ -317,31 +343,31 @@ static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART2CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART3CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART4CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART5CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART6CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
@ -436,6 +462,8 @@ static struct owl_clk_common *s500_clks[] = {
&apb_clk.common,
&dmac_clk.common,
&gpio_clk.common,
&nic_clk.common,
&ethernet_clk.common,
};
static struct clk_hw_onecell_data s500_hw_clks = {
@ -495,6 +523,8 @@ static struct clk_hw_onecell_data s500_hw_clks = {
[CLK_APB] = &apb_clk.common.hw,
[CLK_DMAC] = &dmac_clk.common.hw,
[CLK_GPIO] = &gpio_clk.common.hw,
[CLK_NIC] = &nic_clk.common.hw,
[CLK_ETHERNET] = &ethernet_clk.common.hw,
},
.num = CLK_NR_CLKS,
};

2
drivers/clk/analogbits/wrpll-cln28hpc.c
View File

@ -198,7 +198,7 @@ static int __wrpll_update_parent_rate(struct wrpll_cfg *c,
}
/**
* wrpll_configure() - compute PLL configuration for a target rate
* wrpll_configure_for_rate() - compute PLL configuration for a target rate
* @c: ptr to a struct wrpll_cfg record to write into
* @target_rate: target PLL output clock rate (post-Q-divider)
* @parent_rate: PLL input refclk rate (pre-R-divider)

11
drivers/clk/clk-bd718x7.c
View File

@ -15,15 +15,13 @@
/* clk control registers */
/* BD71815 */
#define BD71815_REG_OUT32K 0x1d
/* BD70528 */
#define BD70528_REG_OUT32K 0x2c
/* BD71828 */
#define BD71828_REG_OUT32K 0x4B
/* BD71837 and BD71847 */
#define BD718XX_REG_OUT32K 0x2E
/*
* BD71837, BD71847, BD70528 and BD71828 all use bit [0] to clk output control
* BD71837, BD71847, and BD71828 all use bit [0] to clk output control
*/
#define CLK_OUT_EN_MASK BIT(0)
@ -116,10 +114,6 @@ static int bd71837_clk_probe(struct platform_device *pdev)
c->reg = BD71828_REG_OUT32K;
c->mask = CLK_OUT_EN_MASK;
break;
case ROHM_CHIP_TYPE_BD70528:
c->reg = BD70528_REG_OUT32K;
c->mask = CLK_OUT_EN_MASK;
break;
case ROHM_CHIP_TYPE_BD71815:
c->reg = BD71815_REG_OUT32K;
c->mask = CLK_OUT_EN_MASK;
@ -150,7 +144,6 @@ static int bd71837_clk_probe(struct platform_device *pdev)
static const struct platform_device_id bd718x7_clk_id[] = {
{ "bd71837-clk", ROHM_CHIP_TYPE_BD71837 },
{ "bd71847-clk", ROHM_CHIP_TYPE_BD71847 },
{ "bd70528-clk", ROHM_CHIP_TYPE_BD70528 },
{ "bd71828-clk", ROHM_CHIP_TYPE_BD71828 },
{ "bd71815-clk", ROHM_CHIP_TYPE_BD71815 },
{ },
@ -168,6 +161,6 @@ static struct platform_driver bd71837_clk = {
module_platform_driver(bd71837_clk);
MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
MODULE_DESCRIPTION("BD718(15/18/28/37/47/50) and BD70528 chip clk driver");
MODULE_DESCRIPTION("BD718(15/18/28/37/47/50) and chip clk driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:bd718xx-clk");

1599
drivers/clk/clk-lmk04832.c Normal file
View File

File diff suppressed because it is too large Load Diff

324
drivers/clk/clk-si5341.c
View File

@ -19,6 +19,7 @@
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <asm/unaligned.h>
@ -59,6 +60,7 @@ struct clk_si5341_synth {
struct clk_si5341_output {
struct clk_hw hw;
struct clk_si5341 *data;
struct regulator *vddo_reg;
u8 index;
};
#define to_clk_si5341_output(_hw) \
@ -78,12 +80,15 @@ struct clk_si5341 {
u8 num_outputs;
u8 num_synth;
u16 chip_id;
bool xaxb_ext_clk;
bool iovdd_33;
};
#define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
struct clk_si5341_output_config {
u8 out_format_drv_bits;
u8 out_cm_ampl_bits;
u8 vdd_sel_bits;
bool synth_master;
bool always_on;
};
@ -92,12 +97,23 @@ struct clk_si5341_output_config {
#define SI5341_PN_BASE 0x0002
#define SI5341_DEVICE_REV 0x0005
#define SI5341_STATUS 0x000C
#define SI5341_LOS 0x000D
#define SI5341_STATUS_STICKY 0x0011
#define SI5341_LOS_STICKY 0x0012
#define SI5341_SOFT_RST 0x001C
#define SI5341_IN_SEL 0x0021
#define SI5341_DEVICE_READY 0x00FE
#define SI5341_XAXB_CFG 0x090E
#define SI5341_IO_VDD_SEL 0x0943
#define SI5341_IN_EN 0x0949
#define SI5341_INX_TO_PFD_EN 0x094A
/* Status bits */
#define SI5341_STATUS_SYSINCAL BIT(0)
#define SI5341_STATUS_LOSXAXB BIT(1)
#define SI5341_STATUS_LOSREF BIT(2)
#define SI5341_STATUS_LOL BIT(3)
/* Input selection */
#define SI5341_IN_SEL_MASK 0x06
#define SI5341_IN_SEL_SHIFT 1
@ -126,6 +142,8 @@ struct clk_si5341_output_config {
#define SI5341_OUT_R_REG(output) \
((output)->data->reg_rdiv_offset[(output)->index])
#define SI5341_OUT_MUX_VDD_SEL_MASK 0x38
/* Synthesize N divider */
#define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
#define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
@ -335,11 +353,12 @@ static const struct si5341_reg_default si5341_reg_defaults[] = {
{ 0x0804, 0x00 }, /* Not in datasheet */
{ 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
{ 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
{ 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */
{ 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
{ 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
{ 0x0A02, 0x00 }, /* Not in datasheet */
{ 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
{ 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */
{ 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */
};
/* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
@ -512,9 +531,11 @@ static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
if (err < 0)
return err;
/* Power up XTAL oscillator and buffer */
/* Power up XTAL oscillator and buffer, select clock mode */
err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
SI5341_XAXB_CFG_PDNB, SI5341_XAXB_CFG_PDNB);
SI5341_XAXB_CFG_PDNB | SI5341_XAXB_CFG_EXTCLK_EN,
SI5341_XAXB_CFG_PDNB | (data->xaxb_ext_clk ?
SI5341_XAXB_CFG_EXTCLK_EN : 0));
if (err < 0)
return err;
}
@ -623,6 +644,9 @@ static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
if (err < 0)
return err;
/* Check for bogus/uninitialized settings */
if (!n_num || !n_den)
return 0;
/*
* n_num and n_den are shifted left as much as possible, so to prevent
@ -806,6 +830,9 @@ static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
{
unsigned long r;
if (!rate)
return 0;
r = *parent_rate >> 1;
/* If rate is an even divisor, no changes to parent required */
@ -834,11 +861,16 @@ static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_si5341_output *output = to_clk_si5341_output(hw);
/* Frequency divider is (r_div + 1) * 2 */
u32 r_div = (parent_rate / rate) >> 1;
u32 r_div;
int err;
u8 r[3];
if (!rate)
return -EINVAL;
/* Frequency divider is (r_div + 1) * 2 */
r_div = (parent_rate / rate) >> 1;
if (r_div <= 1)
r_div = 0;
else if (r_div >= BIT(24))
@ -1083,7 +1115,7 @@ static const struct si5341_reg_default si5341_preamble[] = {
{ 0x0B25, 0x00 },
{ 0x0502, 0x01 },
{ 0x0505, 0x03 },
{ 0x0957, 0x1F },
{ 0x0957, 0x17 },
{ 0x0B4E, 0x1A },
};
@ -1129,6 +1161,11 @@ static int si5341_finalize_defaults(struct clk_si5341 *data)
int res;
u32 revision;
res = regmap_write(data->regmap, SI5341_IO_VDD_SEL,
data->iovdd_33 ? 1 : 0);
if (res < 0)
return res;
res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
if (res < 0)
return res;
@ -1189,6 +1226,32 @@ static const struct regmap_range_cfg si5341_regmap_ranges[] = {
},
};
static int si5341_wait_device_ready(struct i2c_client *client)
{
int count;
/* Datasheet warns: Any attempt to read or write any register other
* than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the
* NVM programming and may corrupt the register contents, as they are
* read from NVM. Note that this includes accesses to the PAGE register.
* Also: DEVICE_READY is available on every register page, so no page
* change is needed to read it.
* Do this outside regmap to avoid automatic PAGE register access.
* May take up to 300ms to complete.
*/
for (count = 0; count < 15; ++count) {
s32 result = i2c_smbus_read_byte_data(client,
SI5341_DEVICE_READY);
if (result < 0)
return result;
if (result == 0x0F)
return 0;
msleep(20);
}
dev_err(&client->dev, "timeout waiting for DEVICE_READY\n");
return -EIO;
}
static const struct regmap_config si5341_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
@ -1199,11 +1262,11 @@ static const struct regmap_config si5341_regmap_config = {
.volatile_table = &si5341_regmap_volatile,
};
static int si5341_dt_parse_dt(struct i2c_client *client,
struct clk_si5341_output_config *config)
static int si5341_dt_parse_dt(struct clk_si5341 *data,
struct clk_si5341_output_config *config)
{
struct device_node *child;
struct device_node *np = client->dev.of_node;
struct device_node *np = data->i2c_client->dev.of_node;
u32 num;
u32 val;
@ -1212,13 +1275,13 @@ static int si5341_dt_parse_dt(struct i2c_client *client,
for_each_child_of_node(np, child) {
if (of_property_read_u32(child, "reg", &num)) {
dev_err(&client->dev, "missing reg property of %s\n",
dev_err(&data->i2c_client->dev, "missing reg property of %s\n",
child->name);
goto put_child;
}
if (num >= SI5341_MAX_NUM_OUTPUTS) {
dev_err(&client->dev, "invalid clkout %d\n", num);
dev_err(&data->i2c_client->dev, "invalid clkout %d\n", num);
goto put_child;
}
@ -1237,7 +1300,7 @@ static int si5341_dt_parse_dt(struct i2c_client *client,
config[num].out_format_drv_bits |= 0xc0;
break;
default:
dev_err(&client->dev,
dev_err(&data->i2c_client->dev,
"invalid silabs,format %u for %u\n",
val, num);
goto put_child;
@ -1250,7 +1313,7 @@ static int si5341_dt_parse_dt(struct i2c_client *client,
if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
if (val > 0xf) {
dev_err(&client->dev,
dev_err(&data->i2c_client->dev,
"invalid silabs,common-mode %u\n",
val);
goto put_child;
@ -1261,7 +1324,7 @@ static int si5341_dt_parse_dt(struct i2c_client *client,
if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
if (val > 0xf) {
dev_err(&client->dev,
dev_err(&data->i2c_client->dev,
"invalid silabs,amplitude %u\n",
val);
goto put_child;
@ -1278,6 +1341,34 @@ static int si5341_dt_parse_dt(struct i2c_client *client,
config[num].always_on =
of_property_read_bool(child, "always-on");
config[num].vdd_sel_bits = 0x08;
if (data->clk[num].vddo_reg) {
int vdd = regulator_get_voltage(data->clk[num].vddo_reg);
switch (vdd) {
case 3300000:
config[num].vdd_sel_bits |= 0 << 4;
break;
case 1800000:
config[num].vdd_sel_bits |= 1 << 4;
break;
case 2500000:
config[num].vdd_sel_bits |= 2 << 4;
break;
default:
dev_err(&data->i2c_client->dev,
"unsupported vddo voltage %d for %s\n",
vdd, child->name);
goto put_child;
}
} else {
/* chip seems to default to 2.5V when not set */
dev_warn(&data->i2c_client->dev,
"no regulator set, defaulting vdd_sel to 2.5V for %s\n",
child->name);
config[num].vdd_sel_bits |= 2 << 4;
}
}
return 0;
@ -1366,6 +1457,94 @@ static int si5341_clk_select_active_input(struct clk_si5341 *data)
return res;
}
static ssize_t input_present_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct clk_si5341 *data = dev_get_drvdata(dev);
u32 status;
int res = regmap_read(data->regmap, SI5341_STATUS, &status);
if (res < 0)
return res;
res = !(status & SI5341_STATUS_LOSREF);
return snprintf(buf, PAGE_SIZE, "%d\n", res);
}
static DEVICE_ATTR_RO(input_present);
static ssize_t input_present_sticky_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct clk_si5341 *data = dev_get_drvdata(dev);
u32 status;
int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status);
if (res < 0)
return res;
res = !(status & SI5341_STATUS_LOSREF);
return snprintf(buf, PAGE_SIZE, "%d\n", res);
}
static DEVICE_ATTR_RO(input_present_sticky);
static ssize_t pll_locked_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct clk_si5341 *data = dev_get_drvdata(dev);
u32 status;
int res = regmap_read(data->regmap, SI5341_STATUS, &status);
if (res < 0)
return res;
res = !(status & SI5341_STATUS_LOL);
return snprintf(buf, PAGE_SIZE, "%d\n", res);
}
static DEVICE_ATTR_RO(pll_locked);
static ssize_t pll_locked_sticky_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct clk_si5341 *data = dev_get_drvdata(dev);
u32 status;
int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status);
if (res < 0)
return res;
res = !(status & SI5341_STATUS_LOL);
return snprintf(buf, PAGE_SIZE, "%d\n", res);
}
static DEVICE_ATTR_RO(pll_locked_sticky);
static ssize_t clear_sticky_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct clk_si5341 *data = dev_get_drvdata(dev);
long val;
if (kstrtol(buf, 10, &val))
return -EINVAL;
if (val) {
int res = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
if (res < 0)
return res;
}
return count;
}
static DEVICE_ATTR_WO(clear_sticky);
static const struct attribute *si5341_attributes[] = {
&dev_attr_input_present.attr,
&dev_attr_input_present_sticky.attr,
&dev_attr_pll_locked.attr,
&dev_attr_pll_locked_sticky.attr,
&dev_attr_clear_sticky.attr,
NULL
};
static int si5341_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@ -1378,6 +1557,7 @@ static int si5341_probe(struct i2c_client *client,
unsigned int i;
struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
bool initialization_required;
u32 status;
data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
if (!data)
@ -1385,6 +1565,11 @@ static int si5341_probe(struct i2c_client *client,
data->i2c_client = client;
/* Must be done before otherwise touching hardware */
err = si5341_wait_device_ready(client);
if (err)
return err;
for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
if (IS_ERR(input)) {
@ -1397,9 +1582,33 @@ static int si5341_probe(struct i2c_client *client,
}
}
err = si5341_dt_parse_dt(client, config);
for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
char reg_name[10];
snprintf(reg_name, sizeof(reg_name), "vddo%d", i);
data->clk[i].vddo_reg = devm_regulator_get_optional(
&client->dev, reg_name);
if (IS_ERR(data->clk[i].vddo_reg)) {
err = PTR_ERR(data->clk[i].vddo_reg);
data->clk[i].vddo_reg = NULL;
if (err == -ENODEV)
continue;
goto cleanup;
} else {
err = regulator_enable(data->clk[i].vddo_reg);
if (err) {
dev_err(&client->dev,
"failed to enable %s regulator: %d\n",
reg_name, err);
data->clk[i].vddo_reg = NULL;
goto cleanup;
}
}
}
err = si5341_dt_parse_dt(data, config);
if (err)
return err;
goto cleanup;
if (of_property_read_string(client->dev.of_node, "clock-output-names",
&init.name))
@ -1407,34 +1616,40 @@ static int si5341_probe(struct i2c_client *client,
root_clock_name = init.name;
data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
if (IS_ERR(data->regmap))
return PTR_ERR(data->regmap);
if (IS_ERR(data->regmap)) {
err = PTR_ERR(data->regmap);
goto cleanup;
}
i2c_set_clientdata(client, data);
err = si5341_probe_chip_id(data);
if (err < 0)
return err;
goto cleanup;
if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
initialization_required = true;
} else {
err = si5341_is_programmed_already(data);
if (err < 0)
return err;
goto cleanup;
initialization_required = !err;
}
data->xaxb_ext_clk = of_property_read_bool(client->dev.of_node,
"silabs,xaxb-ext-clk");
data->iovdd_33 = of_property_read_bool(client->dev.of_node,
"silabs,iovdd-33");
if (initialization_required) {
/* Populate the regmap cache in preparation for "cache only" */
err = si5341_read_settings(data);
if (err < 0)
return err;
goto cleanup;
err = si5341_send_preamble(data);
if (err < 0)
return err;
goto cleanup;
/*
* We intend to send all 'final' register values in a single
@ -1447,19 +1662,19 @@ static int si5341_probe(struct i2c_client *client,
err = si5341_write_multiple(data, si5341_reg_defaults,
ARRAY_SIZE(si5341_reg_defaults));
if (err < 0)
return err;
goto cleanup;
}
/* Input must be up and running at this point */
err = si5341_clk_select_active_input(data);
if (err < 0)
return err;
goto cleanup;
if (initialization_required) {
/* PLL configuration is required */
err = si5341_initialize_pll(data);
if (err < 0)
return err;
goto cleanup;
}
/* Register the PLL */
@ -1472,7 +1687,7 @@ static int si5341_probe(struct i2c_client *client,
err = devm_clk_hw_register(&client->dev, &data->hw);
if (err) {
dev_err(&client->dev, "clock registration failed\n");
return err;
goto cleanup;
}
init.num_parents = 1;
@ -1509,13 +1724,17 @@ static int si5341_probe(struct i2c_client *client,
regmap_write(data->regmap,
SI5341_OUT_CM(&data->clk[i]),
config[i].out_cm_ampl_bits);
regmap_update_bits(data->regmap,
SI5341_OUT_MUX_SEL(&data->clk[i]),
SI5341_OUT_MUX_VDD_SEL_MASK,
config[i].vdd_sel_bits);
}
err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
kfree(init.name); /* clock framework made a copy of the name */
if (err) {
dev_err(&client->dev,
"output %u registration failed\n", i);
return err;
goto cleanup;
}
if (config[i].always_on)
clk_prepare(data->clk[i].hw.clk);
@ -1525,7 +1744,7 @@ static int si5341_probe(struct i2c_client *client,
data);
if (err) {
dev_err(&client->dev, "unable to add clk provider\n");
return err;
goto cleanup;
}
if (initialization_required) {
@ -1533,11 +1752,33 @@ static int si5341_probe(struct i2c_client *client,
regcache_cache_only(data->regmap, false);
err = regcache_sync(data->regmap);
if (err < 0)
return err;
goto cleanup;
err = si5341_finalize_defaults(data);
if (err < 0)
return err;
goto cleanup;
}
/* wait for device to report input clock present and PLL lock */
err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status,
!(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)),
10000, 250000);
if (err) {
dev_err(&client->dev, "Error waiting for input clock or PLL lock\n");
goto cleanup;
}
/* clear sticky alarm bits from initialization */
err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
if (err) {
dev_err(&client->dev, "unable to clear sticky status\n");
goto cleanup;
}
err = sysfs_create_files(&client->dev.kobj, si5341_attributes);
if (err) {
dev_err(&client->dev, "unable to create sysfs files\n");
goto cleanup;
}
/* Free the names, clk framework makes copies */
@ -1545,6 +1786,28 @@ static int si5341_probe(struct i2c_client *client,
devm_kfree(&client->dev, (void *)synth_clock_names[i]);
return 0;
cleanup:
for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
if (data->clk[i].vddo_reg)
regulator_disable(data->clk[i].vddo_reg);
}
return err;
}
static int si5341_remove(struct i2c_client *client)
{
struct clk_si5341 *data = i2c_get_clientdata(client);
int i;
sysfs_remove_files(&client->dev.kobj, si5341_attributes);
for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
if (data->clk[i].vddo_reg)
regulator_disable(data->clk[i].vddo_reg);
}
return 0;
}
static const struct i2c_device_id si5341_id[] = {
@ -1573,6 +1836,7 @@ static struct i2c_driver si5341_driver = {
.of_match_table = clk_si5341_of_match,
},
.probe = si5341_probe,
.remove = si5341_remove,
.id_table = si5341_id,
};
module_i2c_driver(si5341_driver);

502
drivers/clk/clk-stm32mp1.c
View File

@ -10,8 +10,11 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
@ -245,7 +248,7 @@ static const char * const dsi_src[] = {
};
static const char * const rtc_src[] = {
"off", "ck_lse", "ck_lsi", "ck_hse_rtc"
"off", "ck_lse", "ck_lsi", "ck_hse"
};
static const char * const mco1_src[] = {
@ -469,7 +472,7 @@ static const struct clk_ops mp1_gate_clk_ops = {
.is_enabled = clk_gate_is_enabled,
};
static struct clk_hw *_get_stm32_mux(void __iomem *base,
static struct clk_hw *_get_stm32_mux(struct device *dev, void __iomem *base,
const struct stm32_mux_cfg *cfg,
spinlock_t *lock)
{
@ -478,7 +481,7 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
struct clk_hw *mux_hw;
if (cfg->mmux) {
mmux = kzalloc(sizeof(*mmux), GFP_KERNEL);
mmux = devm_kzalloc(dev, sizeof(*mmux), GFP_KERNEL);
if (!mmux)
return ERR_PTR(-ENOMEM);
@ -493,7 +496,7 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;
} else {
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
@ -509,13 +512,13 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
return mux_hw;
}
static struct clk_hw *_get_stm32_div(void __iomem *base,
static struct clk_hw *_get_stm32_div(struct device *dev, void __iomem *base,
const struct stm32_div_cfg *cfg,
spinlock_t *lock)
{
struct clk_divider *div;
div = kzalloc(sizeof(*div), GFP_KERNEL);
div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
if (!div)
return ERR_PTR(-ENOMEM);
@ -530,16 +533,16 @@ static struct clk_hw *_get_stm32_div(void __iomem *base,
return &div->hw;
}
static struct clk_hw *
_get_stm32_gate(void __iomem *base,
const struct stm32_gate_cfg *cfg, spinlock_t *lock)
static struct clk_hw *_get_stm32_gate(struct device *dev, void __iomem *base,
const struct stm32_gate_cfg *cfg,
spinlock_t *lock)
{
struct stm32_clk_mgate *mgate;
struct clk_gate *gate;
struct clk_hw *gate_hw;
if (cfg->mgate) {
mgate = kzalloc(sizeof(*mgate), GFP_KERNEL);
mgate = devm_kzalloc(dev, sizeof(*mgate), GFP_KERNEL);
if (!mgate)
return ERR_PTR(-ENOMEM);
@ -554,7 +557,7 @@ _get_stm32_gate(void __iomem *base,
gate_hw = &mgate->gate.hw;
} else {
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
@ -592,7 +595,7 @@ clk_stm32_register_gate_ops(struct device *dev,
if (cfg->ops)
init.ops = cfg->ops;
hw = _get_stm32_gate(base, cfg, lock);
hw = _get_stm32_gate(dev, base, cfg, lock);
if (IS_ERR(hw))
return ERR_PTR(-ENOMEM);
@ -623,7 +626,7 @@ clk_stm32_register_composite(struct device *dev,
gate_ops = NULL;
if (cfg->mux) {
mux_hw = _get_stm32_mux(base, cfg->mux, lock);
mux_hw = _get_stm32_mux(dev, base, cfg->mux, lock);
if (!IS_ERR(mux_hw)) {
mux_ops = &clk_mux_ops;
@ -634,7 +637,7 @@ clk_stm32_register_composite(struct device *dev,
}
if (cfg->div) {
div_hw = _get_stm32_div(base, cfg->div, lock);
div_hw = _get_stm32_div(dev, base, cfg->div, lock);
if (!IS_ERR(div_hw)) {
div_ops = &clk_divider_ops;
@ -645,7 +648,7 @@ clk_stm32_register_composite(struct device *dev,
}
if (cfg->gate) {
gate_hw = _get_stm32_gate(base, cfg->gate, lock);
gate_hw = _get_stm32_gate(dev, base, cfg->gate, lock);
if (!IS_ERR(gate_hw)) {
gate_ops = &clk_gate_ops;
@ -731,6 +734,7 @@ struct stm32_pll_obj {
spinlock_t *lock;
void __iomem *reg;
struct clk_hw hw;
struct clk_mux mux;
};
#define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
@ -745,6 +749,8 @@ struct stm32_pll_obj {
#define FRAC_MASK 0x1FFF
#define FRAC_SHIFT 3
#define FRACLE BIT(16)
#define PLL_MUX_SHIFT 0
#define PLL_MUX_MASK 3
static int __pll_is_enabled(struct clk_hw *hw)
{
@ -856,16 +862,29 @@ static int pll_is_enabled(struct clk_hw *hw)
return ret;
}
static u8 pll_get_parent(struct clk_hw *hw)
{
struct stm32_pll_obj *clk_elem = to_pll(hw);
struct clk_hw *mux_hw = &clk_elem->mux.hw;
__clk_hw_set_clk(mux_hw, hw);
return clk_mux_ops.get_parent(mux_hw);
}
static const struct clk_ops pll_ops = {
.enable = pll_enable,
.disable = pll_disable,
.recalc_rate = pll_recalc_rate,
.is_enabled = pll_is_enabled,
.get_parent = pll_get_parent,
};
static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
const char *parent_name,
const char * const *parent_names,
int num_parents,
void __iomem *reg,
void __iomem *mux_reg,
unsigned long flags,
spinlock_t *lock)
{
@ -874,15 +893,22 @@ static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
struct clk_hw *hw;
int err;
element = kzalloc(sizeof(*element), GFP_KERNEL);
element = devm_kzalloc(dev, sizeof(*element), GFP_KERNEL);
if (!element)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &pll_ops;
init.flags = flags;
init.parent_names = &parent_name;
init.num_parents = 1;
init.parent_names = parent_names;
init.num_parents = num_parents;
element->mux.lock = lock;
element->mux.reg = mux_reg;
element->mux.shift = PLL_MUX_SHIFT;
element->mux.mask = PLL_MUX_MASK;
element->mux.flags = CLK_MUX_READ_ONLY;
element->mux.reg = mux_reg;
element->hw.init = &init;
element->reg = reg;
@ -891,10 +917,8 @@ static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
hw = &element->hw;
err = clk_hw_register(dev, hw);
if (err) {
kfree(element);
if (err)
return ERR_PTR(err);
}
return hw;
}
@ -1005,7 +1029,7 @@ static struct clk_hw *clk_register_cktim(struct device *dev, const char *name,
struct clk_hw *hw;
int err;
tim_ker = kzalloc(sizeof(*tim_ker), GFP_KERNEL);
tim_ker = devm_kzalloc(dev, sizeof(*tim_ker), GFP_KERNEL);
if (!tim_ker)
return ERR_PTR(-ENOMEM);
@ -1023,16 +1047,56 @@ static struct clk_hw *clk_register_cktim(struct device *dev, const char *name,
hw = &tim_ker->hw;
err = clk_hw_register(dev, hw);
if (err) {
kfree(tim_ker);
if (err)
return ERR_PTR(err);
}
return hw;
}
/* The divider of RTC clock concerns only ck_hse clock */
#define HSE_RTC 3
static unsigned long clk_divider_rtc_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
return clk_divider_ops.recalc_rate(hw, parent_rate);
return parent_rate;
}
static int clk_divider_rtc_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
return clk_divider_ops.set_rate(hw, rate, parent_rate);
return parent_rate;
}
static int clk_divider_rtc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
unsigned long best_parent_rate = req->best_parent_rate;
if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC)) {
req->rate = clk_divider_ops.round_rate(hw, req->rate, &best_parent_rate);
req->best_parent_rate = best_parent_rate;
} else {
req->rate = best_parent_rate;
}
return 0;
}
static const struct clk_ops rtc_div_clk_ops = {
.recalc_rate = clk_divider_rtc_recalc_rate,
.set_rate = clk_divider_rtc_set_rate,
.determine_rate = clk_divider_rtc_determine_rate
};
struct stm32_pll_cfg {
u32 offset;
u32 muxoff;
};
static struct clk_hw *_clk_register_pll(struct device *dev,
@ -1042,8 +1106,11 @@ static struct clk_hw *_clk_register_pll(struct device *dev,
{
struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
return clk_register_pll(dev, cfg->name, cfg->parent_name,
base + stm_pll_cfg->offset, cfg->flags, lock);
return clk_register_pll(dev, cfg->name, cfg->parent_names,
cfg->num_parents,
base + stm_pll_cfg->offset,
base + stm_pll_cfg->muxoff,
cfg->flags, lock);
}
struct stm32_cktim_cfg {
@ -1153,14 +1220,16 @@ _clk_stm32_register_composite(struct device *dev,
.func = _clk_hw_register_mux,\
}
#define PLL(_id, _name, _parent, _flags, _offset)\
#define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\
{\
.id = _id,\
.name = _name,\
.parent_name = _parent,\
.flags = _flags,\
.parent_names = _parents,\
.num_parents = ARRAY_SIZE(_parents),\
.flags = CLK_IGNORE_UNUSED | (_flags),\
.cfg = &(struct stm32_pll_cfg) {\
.offset = _offset,\
.offset = _offset_p,\
.muxoff = _offset_mux,\
},\
.func = _clk_register_pll,\
}
@ -1243,6 +1312,10 @@ _clk_stm32_register_composite(struct device *dev,
_STM32_DIV(_div_offset, _div_shift, _div_width,\
_div_flags, _div_table, NULL)\
#define _DIV_RTC(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
_STM32_DIV(_div_offset, _div_shift, _div_width,\
_div_flags, _div_table, &rtc_div_clk_ops)
#define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
.mux = &(struct stm32_mux_cfg) {\
&(struct mux_cfg) {\
@ -1657,36 +1730,26 @@ static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
};
static const struct clock_config stm32mp1_clock_cfg[] = {
/* Oscillator divider */
DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY),
/* External / Internal Oscillators */
GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
/* ck_csi is used by IO compensation and should be critical */
GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
RCC_OCENSETR, 4, 0),
GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,
_GATE_MP1(RCC_OCENSETR, 0, 0),
_NO_MUX,
_DIV(RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO |
CLK_DIVIDER_READ_ONLY, NULL)),
GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
/* ref clock pll */
MUX(NO_ID, "ref1", ref12_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK12SELR,
0, 2, CLK_MUX_READ_ONLY),
MUX(NO_ID, "ref3", ref3_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK3SELR,
0, 2, CLK_MUX_READ_ONLY),
MUX(NO_ID, "ref4", ref4_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK4SELR,
0, 2, CLK_MUX_READ_ONLY),
/* PLLs */
PLL(PLL1, "pll1", "ref1", CLK_IGNORE_UNUSED, RCC_PLL1CR),
PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),
PLL(PLL3, "pll3", "ref3", CLK_IGNORE_UNUSED, RCC_PLL3CR),
PLL(PLL4, "pll4", "ref4", CLK_IGNORE_UNUSED, RCC_PLL4CR),
PLL(PLL1, "pll1", ref12_parents, 0, RCC_PLL1CR, RCC_RCK12SELR),
PLL(PLL2, "pll2", ref12_parents, 0, RCC_PLL2CR, RCC_RCK12SELR),
PLL(PLL3, "pll3", ref3_parents, 0, RCC_PLL3CR, RCC_RCK3SELR),
PLL(PLL4, "pll4", ref4_parents, 0, RCC_PLL4CR, RCC_RCK4SELR),
/* ODF */
COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
@ -1965,13 +2028,10 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
_DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
/* RTC clock */
DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
CLK_SET_RATE_PARENT,
COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE,
_GATE(RCC_BDCR, 20, 0),
_MUX(RCC_BDCR, 16, 2, 0),
_NO_DIV),
_DIV_RTC(RCC_RTCDIVR, 0, 6, 0, NULL)),
/* MCO clocks */
COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
@ -1996,16 +2056,76 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
_DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
};
struct stm32_clock_match_data {
static const u32 stm32mp1_clock_secured[] = {
CK_HSE,
CK_HSI,
CK_CSI,
CK_LSI,
CK_LSE,
PLL1,
PLL2,
PLL1_P,
PLL2_P,
PLL2_Q,
PLL2_R,
CK_MPU,
CK_AXI,
SPI6,
I2C4,
I2C6,
USART1,
RTCAPB,
TZC1,
TZC2,
TZPC,
IWDG1,
BSEC,
STGEN,
GPIOZ,
CRYP1,
HASH1,
RNG1,
BKPSRAM,
RNG1_K,
STGEN_K,
SPI6_K,
I2C4_K,
I2C6_K,
USART1_K,
RTC,
};
static bool stm32_check_security(const struct clock_config *cfg)
{
int i;
for (i = 0; i < ARRAY_SIZE(stm32mp1_clock_secured); i++)
if (cfg->id == stm32mp1_clock_secured[i])
return true;
return false;
}
struct stm32_rcc_match_data {
const struct clock_config *cfg;
unsigned int num;
unsigned int maxbinding;
u32 clear_offset;
bool (*check_security)(const struct clock_config *cfg);
};
static struct stm32_clock_match_data stm32mp1_data = {
static struct stm32_rcc_match_data stm32mp1_data = {
.cfg = stm32mp1_clock_cfg,
.num = ARRAY_SIZE(stm32mp1_clock_cfg),
.maxbinding = STM32MP1_LAST_CLK,
.clear_offset = RCC_CLR,
};
static struct stm32_rcc_match_data stm32mp1_data_secure = {
.cfg = stm32mp1_clock_cfg,
.num = ARRAY_SIZE(stm32mp1_clock_cfg),
.maxbinding = STM32MP1_LAST_CLK,
.clear_offset = RCC_CLR,
.check_security = &stm32_check_security
};
static const struct of_device_id stm32mp1_match_data[] = {
@ -2013,8 +2133,13 @@ static const struct of_device_id stm32mp1_match_data[] = {
.compatible = "st,stm32mp1-rcc",
.data = &stm32mp1_data,
},
{
.compatible = "st,stm32mp1-rcc-secure",
.data = &stm32mp1_data_secure,
},
{ }
};
MODULE_DEVICE_TABLE(of, stm32mp1_match_data);
static int stm32_register_hw_clk(struct device *dev,
struct clk_hw_onecell_data *clk_data,
@ -2040,28 +2165,126 @@ static int stm32_register_hw_clk(struct device *dev,
return 0;
}
static int stm32_rcc_init(struct device_node *np,
void __iomem *base,
const struct of_device_id *match_data)
{
struct clk_hw_onecell_data *clk_data;
struct clk_hw **hws;
const struct of_device_id *match;
const struct stm32_clock_match_data *data;
int err, n, max_binding;
#define STM32_RESET_ID_MASK GENMASK(15, 0)
match = of_match_node(match_data, np);
if (!match) {
pr_err("%s: match data not found\n", __func__);
return -ENODEV;
struct stm32_reset_data {
/* reset lock */
spinlock_t lock;
struct reset_controller_dev rcdev;
void __iomem *membase;
u32 clear_offset;
};
static inline struct stm32_reset_data *
to_stm32_reset_data(struct reset_controller_dev *rcdev)
{
return container_of(rcdev, struct stm32_reset_data, rcdev);
}
static int stm32_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
int reg_width = sizeof(u32);
int bank = id / (reg_width * BITS_PER_BYTE);
int offset = id % (reg_width * BITS_PER_BYTE);
if (data->clear_offset) {
void __iomem *addr;
addr = data->membase + (bank * reg_width);
if (!assert)
addr += data->clear_offset;
writel(BIT(offset), addr);
} else {
unsigned long flags;
u32 reg;
spin_lock_irqsave(&data->lock, flags);
reg = readl(data->membase + (bank * reg_width));
if (assert)
reg |= BIT(offset);
else
reg &= ~BIT(offset);
writel(reg, data->membase + (bank * reg_width));
spin_unlock_irqrestore(&data->lock, flags);
}
return 0;
}
static int stm32_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return stm32_reset_update(rcdev, id, true);
}
static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return stm32_reset_update(rcdev, id, false);
}
static int stm32_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
int reg_width = sizeof(u32);
int bank = id / (reg_width * BITS_PER_BYTE);
int offset = id % (reg_width * BITS_PER_BYTE);
u32 reg;
reg = readl(data->membase + (bank * reg_width));
return !!(reg & BIT(offset));
}
static const struct reset_control_ops stm32_reset_ops = {
.assert = stm32_reset_assert,
.deassert = stm32_reset_deassert,
.status = stm32_reset_status,
};
static int stm32_rcc_reset_init(struct device *dev, void __iomem *base,
const struct of_device_id *match)
{
const struct stm32_rcc_match_data *data = match->data;
struct stm32_reset_data *reset_data = NULL;
data = match->data;
reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
if (!reset_data)
return -ENOMEM;
reset_data->membase = base;
reset_data->rcdev.owner = THIS_MODULE;
reset_data->rcdev.ops = &stm32_reset_ops;
reset_data->rcdev.of_node = dev_of_node(dev);
reset_data->rcdev.nr_resets = STM32_RESET_ID_MASK;
reset_data->clear_offset = data->clear_offset;
return reset_controller_register(&reset_data->rcdev);
}
static int stm32_rcc_clock_init(struct device *dev, void __iomem *base,
const struct of_device_id *match)
{
const struct stm32_rcc_match_data *data = match->data;
struct clk_hw_onecell_data *clk_data;
struct clk_hw **hws;
int err, n, max_binding;
max_binding = data->maxbinding;
clk_data = kzalloc(struct_size(clk_data, hws, max_binding),
GFP_KERNEL);
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding),
GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
@ -2073,36 +2296,139 @@ static int stm32_rcc_init(struct device_node *np,
hws[n] = ERR_PTR(-ENOENT);
for (n = 0; n < data->num; n++) {
err = stm32_register_hw_clk(NULL, clk_data, base, &rlock,
if (data->check_security && data->check_security(&data->cfg[n]))
continue;
err = stm32_register_hw_clk(dev, clk_data, base, &rlock,
&data->cfg[n]);
if (err) {
pr_err("%s: can't register %s\n", __func__,
data->cfg[n].name);
kfree(clk_data);
dev_err(dev, "Can't register clk %s: %d\n",
data->cfg[n].name, err);
return err;
}
}
return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
return of_clk_add_hw_provider(dev_of_node(dev), of_clk_hw_onecell_get, clk_data);
}
static void stm32mp1_rcc_init(struct device_node *np)
static int stm32_rcc_init(struct device *dev, void __iomem *base,
const struct of_device_id *match_data)
{
const struct of_device_id *match;
int err;
match = of_match_node(match_data, dev_of_node(dev));
if (!match) {
dev_err(dev, "match data not found\n");
return -ENODEV;
}
/* RCC Reset Configuration */
err = stm32_rcc_reset_init(dev, base, match);
if (err) {
pr_err("stm32mp1 reset failed to initialize\n");
return err;
}
/* RCC Clock Configuration */
err = stm32_rcc_clock_init(dev, base, match);
if (err) {
pr_err("stm32mp1 clock failed to initialize\n");
return err;
}
return 0;
}
static int stm32mp1_rcc_init(struct device *dev)
{
void __iomem *base;
int ret;
base = of_iomap(np, 0);
base = of_iomap(dev_of_node(dev), 0);
if (!base) {
pr_err("%pOFn: unable to map resource", np);
of_node_put(np);
return;
pr_err("%pOFn: unable to map resource", dev_of_node(dev));
ret = -ENOMEM;
goto out;
}
if (stm32_rcc_init(np, base, stm32mp1_match_data)) {
iounmap(base);
of_node_put(np);
ret = stm32_rcc_init(dev, base, stm32mp1_match_data);
out:
if (ret) {
if (base)
iounmap(base);
of_node_put(dev_of_node(dev));
}
return ret;
}
CLK_OF_DECLARE_DRIVER(stm32mp1_rcc, "st,stm32mp1-rcc", stm32mp1_rcc_init);
static int get_clock_deps(struct device *dev)
{
static const char * const clock_deps_name[] = {
"hsi", "hse", "csi", "lsi", "lse",
};
size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
struct clk **clk_deps;
int i;
clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
if (!clk_deps)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
clock_deps_name[i]);
if (IS_ERR(clk)) {
if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
return PTR_ERR(clk);
} else {
/* Device gets a reference count on the clock */
clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk));
clk_put(clk);
}
}
return 0;
}
static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int ret = get_clock_deps(dev);
if (!ret)
ret = stm32mp1_rcc_init(dev);
return ret;
}
static int stm32mp1_rcc_clocks_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *child, *np = dev_of_node(dev);
for_each_available_child_of_node(np, child)
of_clk_del_provider(child);
return 0;
}
static struct platform_driver stm32mp1_rcc_clocks_driver = {
.driver = {
.name = "stm32mp1_rcc",
.of_match_table = stm32mp1_match_data,
},
.probe = stm32mp1_rcc_clocks_probe,
.remove = stm32mp1_rcc_clocks_remove,
};
static int __init stm32mp1_clocks_init(void)
{
return platform_driver_register(&stm32mp1_rcc_clocks_driver);
}
core_initcall(stm32mp1_clocks_init);

27
drivers/clk/clk-versaclock5.c
View File

@ -69,7 +69,10 @@
#define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n))
#define VC5_RC_CONTROL0 0x1e
#define VC5_RC_CONTROL1 0x1f
/* Register 0x20 is factory reserved */
/* These registers are named "Unused Factory Reserved Registers" */
#define VC5_RESERVED_X0(idx) (0x20 + ((idx) * 0x10))
#define VC5_RESERVED_X0_BYPASS_SYNC BIT(7) /* bypass_sync<idx> bit */
/* Output divider control for divider 1,2,3,4 */
#define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10))
@ -87,7 +90,6 @@
#define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n))
#define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n))
#define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10))
/* Registers 0x30, 0x40, 0x50 are factory reserved */
/* Clock control register for clock 1,2 */
#define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n))
@ -140,6 +142,8 @@
#define VC5_HAS_INTERNAL_XTAL BIT(0)
/* chip has PFD requency doubler */
#define VC5_HAS_PFD_FREQ_DBL BIT(1)
/* chip has bits to disable FOD sync */
#define VC5_HAS_BYPASS_SYNC_BIT BIT(2)
/* Supported IDT VC5 models. */
enum vc5_model {
@ -581,6 +585,23 @@ static int vc5_clk_out_prepare(struct clk_hw *hw)
unsigned int src;
int ret;
/*
* When enabling a FOD, all currently enabled FODs are briefly
* stopped in order to synchronize all of them. This causes a clock
* disruption to any unrelated chips that might be already using
* other clock outputs. Bypass the sync feature to avoid the issue,
* which is possible on the VersaClock 6E family via reserved
* registers.
*/
if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) {
ret = regmap_update_bits(vc5->regmap,
VC5_RESERVED_X0(hwdata->num),
VC5_RESERVED_X0_BYPASS_SYNC,
VC5_RESERVED_X0_BYPASS_SYNC);
if (ret)
return ret;
}
/*
* If the input mux is disabled, enable it first and
* select source from matching FOD.
@ -1166,7 +1187,7 @@ static const struct vc5_chip_info idt_5p49v6965_info = {
.model = IDT_VC6_5P49V6965,
.clk_fod_cnt = 4,
.clk_out_cnt = 5,
.flags = 0,
.flags = VC5_HAS_BYPASS_SYNC_BIT,
};
static const struct i2c_device_id vc5_id[] = {

28
drivers/clk/clkdev.c
View File

@ -190,34 +190,6 @@ vclkdev_create(struct clk_hw *hw, const char *con_id, const char *dev_fmt,
return cl;
}
struct clk_lookup * __ref
clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
{
struct clk_lookup *cl;
va_list ap;
va_start(ap, dev_fmt);
cl = vclkdev_alloc(__clk_get_hw(clk), con_id, dev_fmt, ap);
va_end(ap);
return cl;
}
EXPORT_SYMBOL(clkdev_alloc);
struct clk_lookup *
clkdev_hw_alloc(struct clk_hw *hw, const char *con_id, const char *dev_fmt, ...)
{
struct clk_lookup *cl;
va_list ap;
va_start(ap, dev_fmt);
cl = vclkdev_alloc(hw, con_id, dev_fmt, ap);
va_end(ap);
return cl;
}
EXPORT_SYMBOL(clkdev_hw_alloc);
/**
* clkdev_create - allocate and add a clkdev lookup structure
* @clk: struct clk to associate with all clk_lookups

7
drivers/clk/hisilicon/Kconfig
View File

@ -15,6 +15,13 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
config COMMON_CLK_HI3559A
bool "Hi3559A Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
default ARCH_HISI
help
Build the clock driver for hi3559a.
config COMMON_CLK_HI3660
bool "Hi3660 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST

1
drivers/clk/hisilicon/Makefile
View File

@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
obj-$(CONFIG_COMMON_CLK_HI3559A) += clk-hi3559a.o
obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o
obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o

846
drivers/clk/hisilicon/clk-hi3559a.c Normal file
View File

@ -0,0 +1,846 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Hisilicon Hi3559A clock driver
*
* Copyright (c) 2019-2020, Huawei Tech. Co., Ltd.
*
* Author: Dongjiu Geng <gengdongjiu@huawei.com>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <dt-bindings/clock/hi3559av100-clock.h>
#include "clk.h"
#include "crg.h"
#include "reset.h"
#define CRG_BASE_ADDR 0x18020000
#define PLL_MASK_WIDTH 24
struct hi3559av100_pll_clock {
u32 id;
const char *name;
const char *parent_name;
const u32 ctrl_reg1;
const u8 frac_shift;
const u8 frac_width;
const u8 postdiv1_shift;
const u8 postdiv1_width;
const u8 postdiv2_shift;
const u8 postdiv2_width;
const u32 ctrl_reg2;
const u8 fbdiv_shift;
const u8 fbdiv_width;
const u8 refdiv_shift;
const u8 refdiv_width;
};
struct hi3559av100_clk_pll {
struct clk_hw hw;
u32 id;
void __iomem *ctrl_reg1;
u8 frac_shift;
u8 frac_width;
u8 postdiv1_shift;
u8 postdiv1_width;
u8 postdiv2_shift;
u8 postdiv2_width;
void __iomem *ctrl_reg2;
u8 fbdiv_shift;
u8 fbdiv_width;
u8 refdiv_shift;
u8 refdiv_width;
};
/* soc clk config */
static const struct hisi_fixed_rate_clock hi3559av100_fixed_rate_clks_crg[] = {
{ HI3559AV100_FIXED_1188M, "1188m", NULL, 0, 1188000000, },
{ HI3559AV100_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
{ HI3559AV100_FIXED_842M, "842m", NULL, 0, 842000000, },
{ HI3559AV100_FIXED_792M, "792m", NULL, 0, 792000000, },
{ HI3559AV100_FIXED_750M, "750m", NULL, 0, 750000000, },
{ HI3559AV100_FIXED_710M, "710m", NULL, 0, 710000000, },
{ HI3559AV100_FIXED_680M, "680m", NULL, 0, 680000000, },
{ HI3559AV100_FIXED_667M, "667m", NULL, 0, 667000000, },
{ HI3559AV100_FIXED_631M, "631m", NULL, 0, 631000000, },
{ HI3559AV100_FIXED_600M, "600m", NULL, 0, 600000000, },
{ HI3559AV100_FIXED_568M, "568m", NULL, 0, 568000000, },
{ HI3559AV100_FIXED_500M, "500m", NULL, 0, 500000000, },
{ HI3559AV100_FIXED_475M, "475m", NULL, 0, 475000000, },
{ HI3559AV100_FIXED_428M, "428m", NULL, 0, 428000000, },
{ HI3559AV100_FIXED_400M, "400m", NULL, 0, 400000000, },
{ HI3559AV100_FIXED_396M, "396m", NULL, 0, 396000000, },
{ HI3559AV100_FIXED_300M, "300m", NULL, 0, 300000000, },
{ HI3559AV100_FIXED_250M, "250m", NULL, 0, 250000000, },
{ HI3559AV100_FIXED_200M, "200m", NULL, 0, 200000000, },
{ HI3559AV100_FIXED_198M, "198m", NULL, 0, 198000000, },
{ HI3559AV100_FIXED_187p5M, "187p5m", NULL, 0, 187500000, },
{ HI3559AV100_FIXED_150M, "150m", NULL, 0, 150000000, },
{ HI3559AV100_FIXED_148p5M, "148p5m", NULL, 0, 1485000000, },
{ HI3559AV100_FIXED_125M, "125m", NULL, 0, 125000000, },
{ HI3559AV100_FIXED_107M, "107m", NULL, 0, 107000000, },
{ HI3559AV100_FIXED_100M, "100m", NULL, 0, 100000000, },
{ HI3559AV100_FIXED_99M, "99m", NULL, 0, 99000000, },
{ HI3559AV100_FIXED_75M, "75m", NULL, 0, 75000000, },
{ HI3559AV100_FIXED_74p25M, "74p25m", NULL, 0, 74250000, },
{ HI3559AV100_FIXED_72M, "72m", NULL, 0, 72000000, },
{ HI3559AV100_FIXED_60M, "60m", NULL, 0, 60000000, },
{ HI3559AV100_FIXED_54M, "54m", NULL, 0, 54000000, },
{ HI3559AV100_FIXED_50M, "50m", NULL, 0, 50000000, },
{ HI3559AV100_FIXED_49p5M, "49p5m", NULL, 0, 49500000, },
{ HI3559AV100_FIXED_37p125M, "37p125m", NULL, 0, 37125000, },
{ HI3559AV100_FIXED_36M, "36m", NULL, 0, 36000000, },
{ HI3559AV100_FIXED_32p4M, "32p4m", NULL, 0, 32400000, },
{ HI3559AV100_FIXED_27M, "27m", NULL, 0, 27000000, },
{ HI3559AV100_FIXED_25M, "25m", NULL, 0, 25000000, },
{ HI3559AV100_FIXED_24M, "24m", NULL, 0, 24000000, },
{ HI3559AV100_FIXED_12M, "12m", NULL, 0, 12000000, },
{ HI3559AV100_FIXED_3M, "3m", NULL, 0, 3000000, },
{ HI3559AV100_FIXED_1p6M, "1p6m", NULL, 0, 1600000, },
{ HI3559AV100_FIXED_400K, "400k", NULL, 0, 400000, },
{ HI3559AV100_FIXED_100K, "100k", NULL, 0, 100000, },
};
static const char *fmc_mux_p[] __initconst = {
"24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m"
};
static const char *mmc_mux_p[] __initconst = {
"100k", "25m", "49p5m", "99m", "187p5m", "150m", "198m", "400k"
};
static const char *sysapb_mux_p[] __initconst = {
"24m", "50m",
};
static const char *sysbus_mux_p[] __initconst = {
"24m", "300m"
};
static const char *uart_mux_p[] __initconst = { "50m", "24m", "3m" };
static const char *a73_clksel_mux_p[] __initconst = {
"24m", "apll", "1000m"
};
static const u32 fmc_mux_table[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
static const u32 mmc_mux_table[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
static const u32 sysapb_mux_table[] = { 0, 1 };
static const u32 sysbus_mux_table[] = { 0, 1 };
static const u32 uart_mux_table[] = { 0, 1, 2 };
static const u32 a73_clksel_mux_table[] = { 0, 1, 2 };
static struct hisi_mux_clock hi3559av100_mux_clks_crg[] __initdata = {
{
HI3559AV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
},
{
HI3559AV100_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table,
},
{
HI3559AV100_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table,
},
{
HI3559AV100_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table,
},
{
HI3559AV100_MMC3_MUX, "mmc3_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
CLK_SET_RATE_PARENT, 0x23c, 24, 3, 0, mmc_mux_table,
},
{
HI3559AV100_SYSAPB_MUX, "sysapb_mux", sysapb_mux_p, ARRAY_SIZE(sysapb_mux_p),
CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table
},
{
HI3559AV100_SYSBUS_MUX, "sysbus_mux", sysbus_mux_p, ARRAY_SIZE(sysbus_mux_p),
CLK_SET_RATE_PARENT, 0xe8, 0, 1, 0, sysbus_mux_table
},
{
HI3559AV100_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
CLK_SET_RATE_PARENT, 0x198, 28, 2, 0, uart_mux_table
},
{
HI3559AV100_A73_MUX, "a73_mux", a73_clksel_mux_p, ARRAY_SIZE(a73_clksel_mux_p),
CLK_SET_RATE_PARENT, 0xe4, 0, 2, 0, a73_clksel_mux_table
},
};
static struct hisi_gate_clock hi3559av100_gate_clks[] __initdata = {
{
HI3559AV100_FMC_CLK, "clk_fmc", "fmc_mux",
CLK_SET_RATE_PARENT, 0x170, 1, 0,
},
{
HI3559AV100_MMC0_CLK, "clk_mmc0", "mmc0_mux",
CLK_SET_RATE_PARENT, 0x1a8, 28, 0,
},
{
HI3559AV100_MMC1_CLK, "clk_mmc1", "mmc1_mux",
CLK_SET_RATE_PARENT, 0x1ec, 28, 0,
},
{
HI3559AV100_MMC2_CLK, "clk_mmc2", "mmc2_mux",
CLK_SET_RATE_PARENT, 0x214, 28, 0,
},
{
HI3559AV100_MMC3_CLK, "clk_mmc3", "mmc3_mux",
CLK_SET_RATE_PARENT, 0x23c, 28, 0,
},
{
HI3559AV100_UART0_CLK, "clk_uart0", "uart_mux",
CLK_SET_RATE_PARENT, 0x198, 23, 0,
},
{
HI3559AV100_UART1_CLK, "clk_uart1", "uart_mux",
CLK_SET_RATE_PARENT, 0x198, 24, 0,
},
{
HI3559AV100_UART2_CLK, "clk_uart2", "uart_mux",
CLK_SET_RATE_PARENT, 0x198, 25, 0,
},
{
HI3559AV100_UART3_CLK, "clk_uart3", "uart_mux",
CLK_SET_RATE_PARENT, 0x198, 26, 0,
},
{
HI3559AV100_UART4_CLK, "clk_uart4", "uart_mux",
CLK_SET_RATE_PARENT, 0x198, 27, 0,
},
{
HI3559AV100_ETH_CLK, "clk_eth", NULL,
CLK_SET_RATE_PARENT, 0x0174, 1, 0,
},
{
HI3559AV100_ETH_MACIF_CLK, "clk_eth_macif", NULL,
CLK_SET_RATE_PARENT, 0x0174, 5, 0,
},
{
HI3559AV100_ETH1_CLK, "clk_eth1", NULL,
CLK_SET_RATE_PARENT, 0x0174, 3, 0,
},
{
HI3559AV100_ETH1_MACIF_CLK, "clk_eth1_macif", NULL,
CLK_SET_RATE_PARENT, 0x0174, 7, 0,
},
{
HI3559AV100_I2C0_CLK, "clk_i2c0", "50m",
CLK_SET_RATE_PARENT, 0x01a0, 16, 0,
},
{
HI3559AV100_I2C1_CLK, "clk_i2c1", "50m",
CLK_SET_RATE_PARENT, 0x01a0, 17, 0,
},
{
HI3559AV100_I2C2_CLK, "clk_i2c2", "50m",
CLK_SET_RATE_PARENT, 0x01a0, 18, 0,
},
{
HI3559AV100_I2C3_CLK, "clk_i2c3", "50m",
CLK_SET_RATE_PARENT, 0x01a0, 19, 0,
},
{
HI3559AV100_I2C4_CLK, "clk_i2c4", "50m",
CLK_SET_RATE_PARENT, 0x01a0, 20, 0,
},
{
HI3559AV100_I2C5_CLK, "clk_i2c5", "50m",
CLK_SET_RATE_PARENT, 0x01a0, 21, 0,
},
{
HI3559AV100_I2C6_CLK, "clk_i2c6", "50m",
CLK_SET_RATE_PARENT, 0x01a0, 22, 0,
},
{
HI3559AV100_I2C7_CLK, "clk_i2c7", "50m",
CLK_SET_RATE_PARENT, 0x01a0, 23, 0,
},
{
HI3559AV100_I2C8_CLK, "clk_i2c8", "50m",
CLK_SET_RATE_PARENT, 0x01a0, 24, 0,
},
{
HI3559AV100_I2C9_CLK, "clk_i2c9", "50m",
CLK_SET_RATE_PARENT, 0x01a0, 25, 0,
},
{
HI3559AV100_I2C10_CLK, "clk_i2c10", "50m",
CLK_SET_RATE_PARENT, 0x01a0, 26, 0,
},
{
HI3559AV100_I2C11_CLK, "clk_i2c11", "50m",
CLK_SET_RATE_PARENT, 0x01a0, 27, 0,
},
{
HI3559AV100_SPI0_CLK, "clk_spi0", "100m",
CLK_SET_RATE_PARENT, 0x0198, 16, 0,
},
{
HI3559AV100_SPI1_CLK, "clk_spi1", "100m",
CLK_SET_RATE_PARENT, 0x0198, 17, 0,
},
{
HI3559AV100_SPI2_CLK, "clk_spi2", "100m",
CLK_SET_RATE_PARENT, 0x0198, 18, 0,
},
{
HI3559AV100_SPI3_CLK, "clk_spi3", "100m",
CLK_SET_RATE_PARENT, 0x0198, 19, 0,
},
{
HI3559AV100_SPI4_CLK, "clk_spi4", "100m",
CLK_SET_RATE_PARENT, 0x0198, 20, 0,
},
{
HI3559AV100_SPI5_CLK, "clk_spi5", "100m",
CLK_SET_RATE_PARENT, 0x0198, 21, 0,
},
{
HI3559AV100_SPI6_CLK, "clk_spi6", "100m",
CLK_SET_RATE_PARENT, 0x0198, 22, 0,
},
{
HI3559AV100_EDMAC_AXICLK, "axi_clk_edmac", NULL,
CLK_SET_RATE_PARENT, 0x16c, 6, 0,
},
{
HI3559AV100_EDMAC_CLK, "clk_edmac", NULL,
CLK_SET_RATE_PARENT, 0x16c, 5, 0,
},
{
HI3559AV100_EDMAC1_AXICLK, "axi_clk_edmac1", NULL,
CLK_SET_RATE_PARENT, 0x16c, 9, 0,
},
{
HI3559AV100_EDMAC1_CLK, "clk_edmac1", NULL,
CLK_SET_RATE_PARENT, 0x16c, 8, 0,
},
{
HI3559AV100_VDMAC_CLK, "clk_vdmac", NULL,
CLK_SET_RATE_PARENT, 0x14c, 5, 0,
},
};
static struct hi3559av100_pll_clock hi3559av100_pll_clks[] __initdata = {
{
HI3559AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
0x4, 0, 12, 12, 6
},
{
HI3559AV100_GPLL_CLK, "gpll", NULL, 0x20, 0, 24, 24, 3, 28, 3,
0x24, 0, 12, 12, 6
},
};
#define to_pll_clk(_hw) container_of(_hw, struct hi3559av100_clk_pll, hw)
static void hi3559av100_calc_pll(u32 *frac_val, u32 *postdiv1_val,
u32 *postdiv2_val,
u32 *fbdiv_val, u32 *refdiv_val, u64 rate)
{
u64 rem;
*postdiv1_val = 2;
*postdiv2_val = 1;
rate = rate * ((*postdiv1_val) * (*postdiv2_val));
*frac_val = 0;
rem = do_div(rate, 1000000);
rem = do_div(rate, PLL_MASK_WIDTH);
*fbdiv_val = rate;
*refdiv_val = 1;
rem = rem * (1 << PLL_MASK_WIDTH);
do_div(rem, PLL_MASK_WIDTH);
*frac_val = rem;
}
static int clk_pll_set_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate)
{
struct hi3559av100_clk_pll *clk = to_pll_clk(hw);
u32 frac_val, postdiv1_val, postdiv2_val, fbdiv_val, refdiv_val;
u32 val;
postdiv1_val = postdiv2_val = 0;
hi3559av100_calc_pll(&frac_val, &postdiv1_val, &postdiv2_val,
&fbdiv_val, &refdiv_val, (u64)rate);
val = readl_relaxed(clk->ctrl_reg1);
val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift);
val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift);
val &= ~(((1 << clk->postdiv2_width) - 1) << clk->postdiv2_shift);
val |= frac_val << clk->frac_shift;
val |= postdiv1_val << clk->postdiv1_shift;
val |= postdiv2_val << clk->postdiv2_shift;
writel_relaxed(val, clk->ctrl_reg1);
val = readl_relaxed(clk->ctrl_reg2);
val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift);
val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift);
val |= fbdiv_val << clk->fbdiv_shift;
val |= refdiv_val << clk->refdiv_shift;
writel_relaxed(val, clk->ctrl_reg2);
return 0;
}
static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct hi3559av100_clk_pll *clk = to_pll_clk(hw);
u64 frac_val, fbdiv_val, refdiv_val;
u32 postdiv1_val, postdiv2_val;
u32 val;
u64 tmp, rate;
val = readl_relaxed(clk->ctrl_reg1);
val = val >> clk->frac_shift;
val &= ((1 << clk->frac_width) - 1);
frac_val = val;
val = readl_relaxed(clk->ctrl_reg1);
val = val >> clk->postdiv1_shift;
val &= ((1 << clk->postdiv1_width) - 1);
postdiv1_val = val;
val = readl_relaxed(clk->ctrl_reg1);
val = val >> clk->postdiv2_shift;
val &= ((1 << clk->postdiv2_width) - 1);
postdiv2_val = val;
val = readl_relaxed(clk->ctrl_reg2);
val = val >> clk->fbdiv_shift;
val &= ((1 << clk->fbdiv_width) - 1);
fbdiv_val = val;
val = readl_relaxed(clk->ctrl_reg2);
val = val >> clk->refdiv_shift;
val &= ((1 << clk->refdiv_width) - 1);
refdiv_val = val;
/* rate = 24000000 * (fbdiv + frac / (1<<24) ) / refdiv */
rate = 0;
tmp = 24000000 * fbdiv_val + (24000000 * frac_val) / (1 << 24);
rate += tmp;
do_div(rate, refdiv_val);
do_div(rate, postdiv1_val * postdiv2_val);
return rate;
}
static const struct clk_ops hisi_clk_pll_ops = {
.set_rate = clk_pll_set_rate,
.recalc_rate = clk_pll_recalc_rate,
};
static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
int nums, struct hisi_clock_data *data, struct device *dev)
{
void __iomem *base = data->base;
struct hi3559av100_clk_pll *p_clk = NULL;
struct clk *clk = NULL;
struct clk_init_data init;
int i;
p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL);
if (!p_clk)
return;
for (i = 0; i < nums; i++) {
init.name = clks[i].name;
init.flags = 0;
init.parent_names =
(clks[i].parent_name ? &clks[i].parent_name : NULL);
init.num_parents = (clks[i].parent_name ? 1 : 0);
init.ops = &hisi_clk_pll_ops;
p_clk->ctrl_reg1 = base + clks[i].ctrl_reg1;
p_clk->frac_shift = clks[i].frac_shift;
p_clk->frac_width = clks[i].frac_width;
p_clk->postdiv1_shift = clks[i].postdiv1_shift;
p_clk->postdiv1_width = clks[i].postdiv1_width;
p_clk->postdiv2_shift = clks[i].postdiv2_shift;
p_clk->postdiv2_width = clks[i].postdiv2_width;
p_clk->ctrl_reg2 = base + clks[i].ctrl_reg2;
p_clk->fbdiv_shift = clks[i].fbdiv_shift;
p_clk->fbdiv_width = clks[i].fbdiv_width;
p_clk->refdiv_shift = clks[i].refdiv_shift;
p_clk->refdiv_width = clks[i].refdiv_width;
p_clk->hw.init = &init;
clk = clk_register(NULL, &p_clk->hw);
if (IS_ERR(clk)) {
devm_kfree(dev, p_clk);
dev_err(dev, "%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
data->clk_data.clks[clks[i].id] = clk;
p_clk++;
}
}
static __init struct hisi_clock_data *hi3559av100_clk_register(
struct platform_device *pdev)
{
struct hisi_clock_data *clk_data;
int ret;
clk_data = hisi_clk_alloc(pdev, HI3559AV100_CRG_NR_CLKS);
if (!clk_data)
return ERR_PTR(-ENOMEM);
ret = hisi_clk_register_fixed_rate(hi3559av100_fixed_rate_clks_crg,
ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data);
if (ret)
return ERR_PTR(ret);
hisi_clk_register_pll(hi3559av100_pll_clks,
ARRAY_SIZE(hi3559av100_pll_clks), clk_data, &pdev->dev);
ret = hisi_clk_register_mux(hi3559av100_mux_clks_crg,
ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data);
if (ret)
goto unregister_fixed_rate;
ret = hisi_clk_register_gate(hi3559av100_gate_clks,
ARRAY_SIZE(hi3559av100_gate_clks), clk_data);
if (ret)
goto unregister_mux;
ret = of_clk_add_provider(pdev->dev.of_node,
of_clk_src_onecell_get, &clk_data->clk_data);
if (ret)
goto unregister_gate;
return clk_data;
unregister_gate:
hisi_clk_unregister_gate(hi3559av100_gate_clks,
ARRAY_SIZE(hi3559av100_gate_clks), clk_data);
unregister_mux:
hisi_clk_unregister_mux(hi3559av100_mux_clks_crg,
ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data);
unregister_fixed_rate:
hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg,
ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data);
return ERR_PTR(ret);
}
static __init void hi3559av100_clk_unregister(struct platform_device *pdev)
{
struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
of_clk_del_provider(pdev->dev.of_node);
hisi_clk_unregister_gate(hi3559av100_gate_clks,
ARRAY_SIZE(hi3559av100_gate_clks), crg->clk_data);
hisi_clk_unregister_mux(hi3559av100_mux_clks_crg,
ARRAY_SIZE(hi3559av100_mux_clks_crg), crg->clk_data);
hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg,
ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), crg->clk_data);
}
static const struct hisi_crg_funcs hi3559av100_crg_funcs = {
.register_clks = hi3559av100_clk_register,
.unregister_clks = hi3559av100_clk_unregister,
};
static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[]
__initdata = {
{ HI3559AV100_SHUB_SOURCE_SOC_24M, "clk_source_24M", NULL, 0, 24000000UL, },
{ HI3559AV100_SHUB_SOURCE_SOC_200M, "clk_source_200M", NULL, 0, 200000000UL, },
{ HI3559AV100_SHUB_SOURCE_SOC_300M, "clk_source_300M", NULL, 0, 300000000UL, },
{ HI3559AV100_SHUB_SOURCE_PLL, "clk_source_PLL", NULL, 0, 192000000UL, },
{ HI3559AV100_SHUB_I2C0_CLK, "clk_shub_i2c0", NULL, 0, 48000000UL, },
{ HI3559AV100_SHUB_I2C1_CLK, "clk_shub_i2c1", NULL, 0, 48000000UL, },
{ HI3559AV100_SHUB_I2C2_CLK, "clk_shub_i2c2", NULL, 0, 48000000UL, },
{ HI3559AV100_SHUB_I2C3_CLK, "clk_shub_i2c3", NULL, 0, 48000000UL, },
{ HI3559AV100_SHUB_I2C4_CLK, "clk_shub_i2c4", NULL, 0, 48000000UL, },
{ HI3559AV100_SHUB_I2C5_CLK, "clk_shub_i2c5", NULL, 0, 48000000UL, },
{ HI3559AV100_SHUB_I2C6_CLK, "clk_shub_i2c6", NULL, 0, 48000000UL, },
{ HI3559AV100_SHUB_I2C7_CLK, "clk_shub_i2c7", NULL, 0, 48000000UL, },
{ HI3559AV100_SHUB_UART_CLK_32K, "clk_uart_32K", NULL, 0, 32000UL, },
};
/* shub mux clk */
static u32 shub_source_clk_mux_table[] = {0, 1, 2, 3};
static const char *shub_source_clk_mux_p[] __initconst = {
"clk_source_24M", "clk_source_200M", "clk_source_300M", "clk_source_PLL"
};
static u32 shub_uart_source_clk_mux_table[] = {0, 1, 2, 3};
static const char *shub_uart_source_clk_mux_p[] __initconst = {
"clk_uart_32K", "clk_uart_div_clk", "clk_uart_div_clk", "clk_source_24M"
};
static struct hisi_mux_clock hi3559av100_shub_mux_clks[] __initdata = {
{
HI3559AV100_SHUB_SOURCE_CLK, "shub_clk", shub_source_clk_mux_p,
ARRAY_SIZE(shub_source_clk_mux_p),
0, 0x0, 0, 2, 0, shub_source_clk_mux_table,
},
{
HI3559AV100_SHUB_UART_SOURCE_CLK, "shub_uart_source_clk",
shub_uart_source_clk_mux_p, ARRAY_SIZE(shub_uart_source_clk_mux_p),
0, 0x1c, 28, 2, 0, shub_uart_source_clk_mux_table,
},
};
/* shub div clk */
static struct clk_div_table shub_spi_clk_table[] = {{0, 8}, {1, 4}, {2, 2}};
static struct clk_div_table shub_uart_div_clk_table[] = {{1, 8}, {2, 4}};
static struct hisi_divider_clock hi3559av100_shub_div_clks[] __initdata = {
{ HI3559AV100_SHUB_SPI_SOURCE_CLK, "clk_spi_clk", "shub_clk", 0, 0x20, 24, 2,
CLK_DIVIDER_ALLOW_ZERO, shub_spi_clk_table,
},
{ HI3559AV100_SHUB_UART_DIV_CLK, "clk_uart_div_clk", "shub_clk", 0, 0x1c, 28, 2,
CLK_DIVIDER_ALLOW_ZERO, shub_uart_div_clk_table,
},
};
/* shub gate clk */
static struct hisi_gate_clock hi3559av100_shub_gate_clks[] __initdata = {
{
HI3559AV100_SHUB_SPI0_CLK, "clk_shub_spi0", "clk_spi_clk",
0, 0x20, 1, 0,
},
{
HI3559AV100_SHUB_SPI1_CLK, "clk_shub_spi1", "clk_spi_clk",
0, 0x20, 5, 0,
},
{
HI3559AV100_SHUB_SPI2_CLK, "clk_shub_spi2", "clk_spi_clk",
0, 0x20, 9, 0,
},
{
HI3559AV100_SHUB_UART0_CLK, "clk_shub_uart0", "shub_uart_source_clk",
0, 0x1c, 1, 0,
},
{
HI3559AV100_SHUB_UART1_CLK, "clk_shub_uart1", "shub_uart_source_clk",
0, 0x1c, 5, 0,
},
{
HI3559AV100_SHUB_UART2_CLK, "clk_shub_uart2", "shub_uart_source_clk",
0, 0x1c, 9, 0,
},
{
HI3559AV100_SHUB_UART3_CLK, "clk_shub_uart3", "shub_uart_source_clk",
0, 0x1c, 13, 0,
},
{
HI3559AV100_SHUB_UART4_CLK, "clk_shub_uart4", "shub_uart_source_clk",
0, 0x1c, 17, 0,
},
{
HI3559AV100_SHUB_UART5_CLK, "clk_shub_uart5", "shub_uart_source_clk",
0, 0x1c, 21, 0,
},
{
HI3559AV100_SHUB_UART6_CLK, "clk_shub_uart6", "shub_uart_source_clk",
0, 0x1c, 25, 0,
},
{
HI3559AV100_SHUB_EDMAC_CLK, "clk_shub_dmac", "shub_clk",
0, 0x24, 4, 0,
},
};
static int hi3559av100_shub_default_clk_set(void)
{
void __iomem *crg_base;
unsigned int val;
crg_base = ioremap(CRG_BASE_ADDR, SZ_4K);
/* SSP: 192M/2 */
val = readl_relaxed(crg_base + 0x20);
val |= (0x2 << 24);
writel_relaxed(val, crg_base + 0x20);
/* UART: 192M/8 */
val = readl_relaxed(crg_base + 0x1C);
val |= (0x1 << 28);
writel_relaxed(val, crg_base + 0x1C);
iounmap(crg_base);
crg_base = NULL;
return 0;
}
static __init struct hisi_clock_data *hi3559av100_shub_clk_register(
struct platform_device *pdev)
{
struct hisi_clock_data *clk_data = NULL;
int ret;
hi3559av100_shub_default_clk_set();
clk_data = hisi_clk_alloc(pdev, HI3559AV100_SHUB_NR_CLKS);
if (!clk_data)
return ERR_PTR(-ENOMEM);
ret = hisi_clk_register_fixed_rate(hi3559av100_shub_fixed_rate_clks,
ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data);
if (ret)
return ERR_PTR(ret);
ret = hisi_clk_register_mux(hi3559av100_shub_mux_clks,
ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data);
if (ret)
goto unregister_fixed_rate;
ret = hisi_clk_register_divider(hi3559av100_shub_div_clks,
ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data);
if (ret)
goto unregister_mux;
ret = hisi_clk_register_gate(hi3559av100_shub_gate_clks,
ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data);
if (ret)
goto unregister_factor;
ret = of_clk_add_provider(pdev->dev.of_node,
of_clk_src_onecell_get, &clk_data->clk_data);
if (ret)
goto unregister_gate;
return clk_data;
unregister_gate:
hisi_clk_unregister_gate(hi3559av100_shub_gate_clks,
ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data);
unregister_factor:
hisi_clk_unregister_divider(hi3559av100_shub_div_clks,
ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data);
unregister_mux:
hisi_clk_unregister_mux(hi3559av100_shub_mux_clks,
ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data);
unregister_fixed_rate:
hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks,
ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data);
return ERR_PTR(ret);
}
static __init void hi3559av100_shub_clk_unregister(struct platform_device *pdev)
{
struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
of_clk_del_provider(pdev->dev.of_node);
hisi_clk_unregister_gate(hi3559av100_shub_gate_clks,
ARRAY_SIZE(hi3559av100_shub_gate_clks), crg->clk_data);
hisi_clk_unregister_divider(hi3559av100_shub_div_clks,
ARRAY_SIZE(hi3559av100_shub_div_clks), crg->clk_data);
hisi_clk_unregister_mux(hi3559av100_shub_mux_clks,
ARRAY_SIZE(hi3559av100_shub_mux_clks), crg->clk_data);
hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks,
ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), crg->clk_data);
}
static const struct hisi_crg_funcs hi3559av100_shub_crg_funcs = {
.register_clks = hi3559av100_shub_clk_register,
.unregister_clks = hi3559av100_shub_clk_unregister,
};
static const struct of_device_id hi3559av100_crg_match_table[] = {
{
.compatible = "hisilicon,hi3559av100-clock",
.data = &hi3559av100_crg_funcs
},
{
.compatible = "hisilicon,hi3559av100-shub-clock",
.data = &hi3559av100_shub_crg_funcs
},
{ }
};
MODULE_DEVICE_TABLE(of, hi3559av100_crg_match_table);
static int hi3559av100_crg_probe(struct platform_device *pdev)
{
struct hisi_crg_dev *crg;
crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
if (!crg)
return -ENOMEM;
crg->funcs = of_device_get_match_data(&pdev->dev);
if (!crg->funcs)
return -ENOENT;
crg->rstc = hisi_reset_init(pdev);
if (!crg->rstc)
return -ENOMEM;
crg->clk_data = crg->funcs->register_clks(pdev);
if (IS_ERR(crg->clk_data)) {
hisi_reset_exit(crg->rstc);
return PTR_ERR(crg->clk_data);
}
platform_set_drvdata(pdev, crg);
return 0;
}
static int hi3559av100_crg_remove(struct platform_device *pdev)
{
struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
hisi_reset_exit(crg->rstc);
crg->funcs->unregister_clks(pdev);
return 0;
}
static struct platform_driver hi3559av100_crg_driver = {
.probe = hi3559av100_crg_probe,
.remove = hi3559av100_crg_remove,
.driver = {
.name = "hi3559av100-clock",
.of_match_table = hi3559av100_crg_match_table,
},
};
static int __init hi3559av100_crg_init(void)
{
return platform_driver_register(&hi3559av100_crg_driver);
}
core_initcall(hi3559av100_crg_init);
static void __exit hi3559av100_crg_exit(void)
{
platform_driver_unregister(&hi3559av100_crg_driver);
}
module_exit(hi3559av100_crg_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("HiSilicon Hi3559AV100 CRG Driver");

2
drivers/clk/hisilicon/clk.c
View File

@ -162,7 +162,7 @@ int hisi_clk_register_mux(const struct hisi_mux_clock *clks,
clks[i].num_parents, clks[i].flags,
base + clks[i].offset, clks[i].shift,
mask, clks[i].mux_flags,
clks[i].table, &hisi_clk_lock);
(u32 *)clks[i].table, &hisi_clk_lock);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);

2
drivers/clk/hisilicon/clk.h
View File

@ -50,7 +50,7 @@ struct hisi_mux_clock {
u8 shift;
u8 width;
u8 mux_flags;
u32 *table;
const u32 *table;
const char *alias;
};

3
drivers/clk/imx/Makefile
View File

@ -27,7 +27,8 @@ obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o
clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o
clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
obj-$(CONFIG_CLK_IMX1) += clk-imx1.o

1
drivers/clk/imx/clk-imx8mp.c
View File

@ -556,7 +556,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);
hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
hws[IMX8MP_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", ccm_base + 0x9180, 0, 1);
hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);

56
drivers/clk/imx/clk-imx8mq.c
View File

@ -358,46 +358,26 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
hws[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_hw_sscg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0);
/* SYS PLL1 fixed output */
hws[IMX8MQ_SYS1_PLL_40M_CG] = imx_clk_hw_gate("sys1_pll_40m_cg", "sys1_pll_out", base + 0x30, 9);
hws[IMX8MQ_SYS1_PLL_80M_CG] = imx_clk_hw_gate("sys1_pll_80m_cg", "sys1_pll_out", base + 0x30, 11);
hws[IMX8MQ_SYS1_PLL_100M_CG] = imx_clk_hw_gate("sys1_pll_100m_cg", "sys1_pll_out", base + 0x30, 13);
hws[IMX8MQ_SYS1_PLL_133M_CG] = imx_clk_hw_gate("sys1_pll_133m_cg", "sys1_pll_out", base + 0x30, 15);
hws[IMX8MQ_SYS1_PLL_160M_CG] = imx_clk_hw_gate("sys1_pll_160m_cg", "sys1_pll_out", base + 0x30, 17);
hws[IMX8MQ_SYS1_PLL_200M_CG] = imx_clk_hw_gate("sys1_pll_200m_cg", "sys1_pll_out", base + 0x30, 19);
hws[IMX8MQ_SYS1_PLL_266M_CG] = imx_clk_hw_gate("sys1_pll_266m_cg", "sys1_pll_out", base + 0x30, 21);
hws[IMX8MQ_SYS1_PLL_400M_CG] = imx_clk_hw_gate("sys1_pll_400m_cg", "sys1_pll_out", base + 0x30, 23);
hws[IMX8MQ_SYS1_PLL_800M_CG] = imx_clk_hw_gate("sys1_pll_800m_cg", "sys1_pll_out", base + 0x30, 25);
hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_40m_cg", 1, 20);
hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_80m_cg", 1, 10);
hws[IMX8MQ_SYS1_PLL_100M] = imx_clk_hw_fixed_factor("sys1_pll_100m", "sys1_pll_100m_cg", 1, 8);
hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_133m_cg", 1, 6);
hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_160m_cg", 1, 5);
hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_200m_cg", 1, 4);
hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_266m_cg", 1, 3);
hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_400m_cg", 1, 2);
hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_800m_cg", 1, 1);
hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20);
hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10);
hws[IMX8MQ_SYS1_PLL_100M] = imx_clk_hw_fixed_factor("sys1_pll_100m", "sys1_pll_out", 1, 8);
hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_out", 1, 6);
hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_out", 1, 5);
hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_out", 1, 4);
hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3);
hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2);
hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1);
/* SYS PLL2 fixed output */
hws[IMX8MQ_SYS2_PLL_50M_CG] = imx_clk_hw_gate("sys2_pll_50m_cg", "sys2_pll_out", base + 0x3c, 9);
hws[IMX8MQ_SYS2_PLL_100M_CG] = imx_clk_hw_gate("sys2_pll_100m_cg", "sys2_pll_out", base + 0x3c, 11);
hws[IMX8MQ_SYS2_PLL_125M_CG] = imx_clk_hw_gate("sys2_pll_125m_cg", "sys2_pll_out", base + 0x3c, 13);
hws[IMX8MQ_SYS2_PLL_166M_CG] = imx_clk_hw_gate("sys2_pll_166m_cg", "sys2_pll_out", base + 0x3c, 15);
hws[IMX8MQ_SYS2_PLL_200M_CG] = imx_clk_hw_gate("sys2_pll_200m_cg", "sys2_pll_out", base + 0x3c, 17);
hws[IMX8MQ_SYS2_PLL_250M_CG] = imx_clk_hw_gate("sys2_pll_250m_cg", "sys2_pll_out", base + 0x3c, 19);
hws[IMX8MQ_SYS2_PLL_333M_CG] = imx_clk_hw_gate("sys2_pll_333m_cg", "sys2_pll_out", base + 0x3c, 21);
hws[IMX8MQ_SYS2_PLL_500M_CG] = imx_clk_hw_gate("sys2_pll_500m_cg", "sys2_pll_out", base + 0x3c, 23);
hws[IMX8MQ_SYS2_PLL_1000M_CG] = imx_clk_hw_gate("sys2_pll_1000m_cg", "sys2_pll_out", base + 0x3c, 25);
hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_50m_cg", 1, 20);
hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_100m_cg", 1, 10);
hws[IMX8MQ_SYS2_PLL_125M] = imx_clk_hw_fixed_factor("sys2_pll_125m", "sys2_pll_125m_cg", 1, 8);
hws[IMX8MQ_SYS2_PLL_166M] = imx_clk_hw_fixed_factor("sys2_pll_166m", "sys2_pll_166m_cg", 1, 6);
hws[IMX8MQ_SYS2_PLL_200M] = imx_clk_hw_fixed_factor("sys2_pll_200m", "sys2_pll_200m_cg", 1, 5);
hws[IMX8MQ_SYS2_PLL_250M] = imx_clk_hw_fixed_factor("sys2_pll_250m", "sys2_pll_250m_cg", 1, 4);
hws[IMX8MQ_SYS2_PLL_333M] = imx_clk_hw_fixed_factor("sys2_pll_333m", "sys2_pll_333m_cg", 1, 3);
hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2);
hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1);
hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20);
hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10);
hws[IMX8MQ_SYS2_PLL_125M] = imx_clk_hw_fixed_factor("sys2_pll_125m", "sys2_pll_out", 1, 8);
hws[IMX8MQ_SYS2_PLL_166M] = imx_clk_hw_fixed_factor("sys2_pll_166m", "sys2_pll_out", 1, 6);
hws[IMX8MQ_SYS2_PLL_200M] = imx_clk_hw_fixed_factor("sys2_pll_200m", "sys2_pll_out", 1, 5);
hws[IMX8MQ_SYS2_PLL_250M] = imx_clk_hw_fixed_factor("sys2_pll_250m", "sys2_pll_out", 1, 4);
hws[IMX8MQ_SYS2_PLL_333M] = imx_clk_hw_fixed_factor("sys2_pll_333m", "sys2_pll_out", 1, 3);
hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_out", 1, 2);
hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_out", 1, 1);
hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3);
hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3);

116
drivers/clk/imx/clk-imx8qm-rsrc.c Normal file
View File

@ -0,0 +1,116 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019-2021 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/firmware/imx/rsrc.h>
#include "clk-scu.h"
/* Keep sorted in the ascending order */
static const u32 imx8qm_clk_scu_rsrc_table[] = {
IMX_SC_R_A53,
IMX_SC_R_A72,
IMX_SC_R_DC_0_VIDEO0,
IMX_SC_R_DC_0_VIDEO1,
IMX_SC_R_DC_0,
IMX_SC_R_DC_0_PLL_0,
IMX_SC_R_DC_0_PLL_1,
IMX_SC_R_DC_1_VIDEO0,
IMX_SC_R_DC_1_VIDEO1,
IMX_SC_R_DC_1,
IMX_SC_R_DC_1_PLL_0,
IMX_SC_R_DC_1_PLL_1,
IMX_SC_R_SPI_0,
IMX_SC_R_SPI_1,
IMX_SC_R_SPI_2,
IMX_SC_R_SPI_3,
IMX_SC_R_UART_0,
IMX_SC_R_UART_1,
IMX_SC_R_UART_2,
IMX_SC_R_UART_3,
IMX_SC_R_UART_4,
IMX_SC_R_EMVSIM_0,
IMX_SC_R_EMVSIM_1,
IMX_SC_R_I2C_0,
IMX_SC_R_I2C_1,
IMX_SC_R_I2C_2,
IMX_SC_R_I2C_3,
IMX_SC_R_I2C_4,
IMX_SC_R_ADC_0,
IMX_SC_R_ADC_1,
IMX_SC_R_FTM_0,
IMX_SC_R_FTM_1,
IMX_SC_R_CAN_0,
IMX_SC_R_GPU_0_PID0,
IMX_SC_R_GPU_1_PID0,
IMX_SC_R_PWM_0,
IMX_SC_R_PWM_1,
IMX_SC_R_PWM_2,
IMX_SC_R_PWM_3,
IMX_SC_R_PWM_4,
IMX_SC_R_PWM_5,
IMX_SC_R_PWM_6,
IMX_SC_R_PWM_7,
IMX_SC_R_GPT_0,
IMX_SC_R_GPT_1,
IMX_SC_R_GPT_2,
IMX_SC_R_GPT_3,
IMX_SC_R_GPT_4,
IMX_SC_R_FSPI_0,
IMX_SC_R_FSPI_1,
IMX_SC_R_SDHC_0,
IMX_SC_R_SDHC_1,
IMX_SC_R_SDHC_2,
IMX_SC_R_ENET_0,
IMX_SC_R_ENET_1,
IMX_SC_R_MLB_0,
IMX_SC_R_USB_2,
IMX_SC_R_NAND,
IMX_SC_R_LVDS_0,
IMX_SC_R_LVDS_0_PWM_0,
IMX_SC_R_LVDS_0_I2C_0,
IMX_SC_R_LVDS_0_I2C_1,
IMX_SC_R_LVDS_1,
IMX_SC_R_LVDS_1_PWM_0,
IMX_SC_R_LVDS_1_I2C_0,
IMX_SC_R_LVDS_1_I2C_1,
IMX_SC_R_M4_0_I2C,
IMX_SC_R_M4_1_I2C,
IMX_SC_R_AUDIO_PLL_0,
IMX_SC_R_VPU_UART,
IMX_SC_R_VPUCORE,
IMX_SC_R_MIPI_0,
IMX_SC_R_MIPI_0_PWM_0,
IMX_SC_R_MIPI_0_I2C_0,
IMX_SC_R_MIPI_0_I2C_1,
IMX_SC_R_MIPI_1,
IMX_SC_R_MIPI_1_PWM_0,
IMX_SC_R_MIPI_1_I2C_0,
IMX_SC_R_MIPI_1_I2C_1,
IMX_SC_R_CSI_0,
IMX_SC_R_CSI_0_PWM_0,
IMX_SC_R_CSI_0_I2C_0,
IMX_SC_R_CSI_1,
IMX_SC_R_CSI_1_PWM_0,
IMX_SC_R_CSI_1_I2C_0,
IMX_SC_R_HDMI,
IMX_SC_R_HDMI_I2S,
IMX_SC_R_HDMI_I2C_0,
IMX_SC_R_HDMI_PLL_0,
IMX_SC_R_HDMI_RX,
IMX_SC_R_HDMI_RX_BYPASS,
IMX_SC_R_HDMI_RX_I2C_0,
IMX_SC_R_AUDIO_PLL_1,
IMX_SC_R_AUDIO_CLK_0,
IMX_SC_R_AUDIO_CLK_1,
IMX_SC_R_HDMI_RX_PWM_0,
IMX_SC_R_HDMI_PLL_1,
IMX_SC_R_VPU,
};
const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm = {
.rsrc = imx8qm_clk_scu_rsrc_table,
.num = ARRAY_SIZE(imx8qm_clk_scu_rsrc_table),
};

89
drivers/clk/imx/clk-imx8qxp-rsrc.c Normal file
View File

@ -0,0 +1,89 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019-2021 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/firmware/imx/rsrc.h>
#include "clk-scu.h"
/* Keep sorted in the ascending order */
static const u32 imx8qxp_clk_scu_rsrc_table[] = {
IMX_SC_R_DC_0_VIDEO0,
IMX_SC_R_DC_0_VIDEO1,
IMX_SC_R_DC_0,
IMX_SC_R_DC_0_PLL_0,
IMX_SC_R_DC_0_PLL_1,
IMX_SC_R_SPI_0,
IMX_SC_R_SPI_1,
IMX_SC_R_SPI_2,
IMX_SC_R_SPI_3,
IMX_SC_R_UART_0,
IMX_SC_R_UART_1,
IMX_SC_R_UART_2,
IMX_SC_R_UART_3,
IMX_SC_R_I2C_0,
IMX_SC_R_I2C_1,
IMX_SC_R_I2C_2,
IMX_SC_R_I2C_3,
IMX_SC_R_ADC_0,
IMX_SC_R_FTM_0,
IMX_SC_R_FTM_1,
IMX_SC_R_CAN_0,
IMX_SC_R_GPU_0_PID0,
IMX_SC_R_LCD_0,
IMX_SC_R_LCD_0_PWM_0,
IMX_SC_R_PWM_0,
IMX_SC_R_PWM_1,
IMX_SC_R_PWM_2,
IMX_SC_R_PWM_3,
IMX_SC_R_PWM_4,
IMX_SC_R_PWM_5,
IMX_SC_R_PWM_6,
IMX_SC_R_PWM_7,
IMX_SC_R_GPT_0,
IMX_SC_R_GPT_1,
IMX_SC_R_GPT_2,
IMX_SC_R_GPT_3,
IMX_SC_R_GPT_4,
IMX_SC_R_FSPI_0,
IMX_SC_R_FSPI_1,
IMX_SC_R_SDHC_0,
IMX_SC_R_SDHC_1,
IMX_SC_R_SDHC_2,
IMX_SC_R_ENET_0,
IMX_SC_R_ENET_1,
IMX_SC_R_MLB_0,
IMX_SC_R_USB_2,
IMX_SC_R_NAND,
IMX_SC_R_LVDS_0,
IMX_SC_R_LVDS_1,
IMX_SC_R_M4_0_I2C,
IMX_SC_R_ELCDIF_PLL,
IMX_SC_R_AUDIO_PLL_0,
IMX_SC_R_PI_0,
IMX_SC_R_PI_0_PLL,
IMX_SC_R_MIPI_0,
IMX_SC_R_MIPI_0_PWM_0,
IMX_SC_R_MIPI_0_I2C_0,
IMX_SC_R_MIPI_0_I2C_1,
IMX_SC_R_MIPI_1,
IMX_SC_R_MIPI_1_PWM_0,
IMX_SC_R_MIPI_1_I2C_0,
IMX_SC_R_MIPI_1_I2C_1,
IMX_SC_R_CSI_0,
IMX_SC_R_CSI_0_PWM_0,
IMX_SC_R_CSI_0_I2C_0,
IMX_SC_R_AUDIO_PLL_1,
IMX_SC_R_AUDIO_CLK_0,
IMX_SC_R_AUDIO_CLK_1,
IMX_SC_R_A35,
IMX_SC_R_VPU_DEC_0,
IMX_SC_R_VPU_ENC_0,
};
const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp = {
.rsrc = imx8qxp_clk_scu_rsrc_table,
.num = ARRAY_SIZE(imx8qxp_clk_scu_rsrc_table),
};

371
drivers/clk/imx/clk-imx8qxp.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
* Copyright 2018-2021 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
@ -9,12 +9,12 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "clk-scu.h"
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/firmware/imx/rsrc.h>
static const char *dc0_sels[] = {
@ -25,159 +25,278 @@ static const char *dc0_sels[] = {
"dc0_bypass0_clk",
};
static const char * const dc1_sels[] = {
"clk_dummy",
"clk_dummy",
"dc1_pll0_clk",
"dc1_pll1_clk",
"dc1_bypass0_clk",
};
static const char * const enet0_rgmii_txc_sels[] = {
"enet0_ref_div",
"clk_dummy",
};
static const char * const enet1_rgmii_txc_sels[] = {
"enet1_ref_div",
"clk_dummy",
};
static const char * const hdmi_sels[] = {
"clk_dummy",
"hdmi_dig_pll_clk",
"clk_dummy",
"clk_dummy",
"hdmi_av_pll_clk",
};
static const char * const hdmi_rx_sels[] = {
"clk_dummy",
"hdmi_rx_dig_pll_clk",
"clk_dummy",
"clk_dummy",
"hdmi_rx_bypass_clk",
};
static const char * const lcd_pxl_sels[] = {
"clk_dummy",
"clk_dummy",
"clk_dummy",
"clk_dummy",
"lcd_pxl_bypass_div_clk",
};
static const char * const mipi_sels[] = {
"clk_dummy",
"clk_dummy",
"mipi_pll_div2_clk",
"clk_dummy",
"clk_dummy",
};
static const char * const lcd_sels[] = {
"clk_dummy",
"clk_dummy",
"clk_dummy",
"clk_dummy",
"elcdif_pll",
};
static const char * const pi_pll0_sels[] = {
"clk_dummy",
"pi_dpll_clk",
"clk_dummy",
"clk_dummy",
"clk_dummy",
};
static int imx8qxp_clk_probe(struct platform_device *pdev)
{
struct device_node *ccm_node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data;
struct clk_hw **clks;
u32 clk_cells;
int ret, i;
const struct imx_clk_scu_rsrc_table *rsrc_table;
int ret;
ret = imx_clk_scu_init(ccm_node);
rsrc_table = of_device_get_match_data(&pdev->dev);
ret = imx_clk_scu_init(ccm_node, rsrc_table);
if (ret)
return ret;
clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
IMX_SCU_CLK_END), GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
if (of_property_read_u32(ccm_node, "#clock-cells", &clk_cells))
return -EINVAL;
clk_data->num = IMX_SCU_CLK_END;
clks = clk_data->hws;
/* Fixed clocks */
clks[IMX_CLK_DUMMY] = clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
clks[IMX_ADMA_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "dma_ipg_clk_root", NULL, 0, 120000000);
clks[IMX_CONN_AXI_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_axi_clk_root", NULL, 0, 333333333);
clks[IMX_CONN_AHB_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ahb_clk_root", NULL, 0, 166666666);
clks[IMX_CONN_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ipg_clk_root", NULL, 0, 83333333);
clks[IMX_DC_AXI_EXT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_ext_clk_root", NULL, 0, 800000000);
clks[IMX_DC_AXI_INT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_int_clk_root", NULL, 0, 400000000);
clks[IMX_DC_CFG_CLK] = clk_hw_register_fixed_rate(NULL, "dc_cfg_clk_root", NULL, 0, 100000000);
clks[IMX_MIPI_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "mipi_ipg_clk_root", NULL, 0, 120000000);
clks[IMX_IMG_AXI_CLK] = clk_hw_register_fixed_rate(NULL, "img_axi_clk_root", NULL, 0, 400000000);
clks[IMX_IMG_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "img_ipg_clk_root", NULL, 0, 200000000);
clks[IMX_IMG_PXL_CLK] = clk_hw_register_fixed_rate(NULL, "img_pxl_clk_root", NULL, 0, 600000000);
clks[IMX_HSIO_AXI_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_axi_clk_root", NULL, 0, 400000000);
clks[IMX_HSIO_PER_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333);
clks[IMX_LSIO_MEM_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 200000000);
clks[IMX_LSIO_BUS_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 100000000);
/* ARM core */
clks[IMX_A35_CLK] = imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU, clk_cells);
imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
imx_clk_scu("a53_clk", IMX_SC_R_A53, IMX_SC_PM_CLK_CPU);
imx_clk_scu("a72_clk", IMX_SC_R_A72, IMX_SC_PM_CLK_CPU);
/* LSIO SS */
clks[IMX_LSIO_PWM0_CLK] = imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_PWM1_CLK] = imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_PWM2_CLK] = imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_PWM3_CLK] = imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_PWM4_CLK] = imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_PWM5_CLK] = imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_PWM6_CLK] = imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_PWM7_CLK] = imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_GPT0_CLK] = imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_GPT1_CLK] = imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_GPT2_CLK] = imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_GPT3_CLK] = imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_GPT4_CLK] = imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_FSPI0_CLK] = imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_FSPI1_CLK] = imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER, clk_cells);
imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER);
imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER);
/* ADMA SS */
clks[IMX_ADMA_UART0_CLK] = imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_UART1_CLK] = imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_UART2_CLK] = imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_UART3_CLK] = imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_SPI0_CLK] = imx_clk_scu("spi0_clk", IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_SPI1_CLK] = imx_clk_scu("spi1_clk", IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_SPI2_CLK] = imx_clk_scu("spi2_clk", IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_SPI3_CLK] = imx_clk_scu("spi3_clk", IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_CAN0_CLK] = imx_clk_scu("can0_clk", IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_I2C0_CLK] = imx_clk_scu("i2c0_clk", IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_I2C1_CLK] = imx_clk_scu("i2c1_clk", IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_I2C2_CLK] = imx_clk_scu("i2c2_clk", IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_I2C3_CLK] = imx_clk_scu("i2c3_clk", IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_FTM0_CLK] = imx_clk_scu("ftm0_clk", IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_FTM1_CLK] = imx_clk_scu("ftm1_clk", IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_ADC0_CLK] = imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_PWM_CLK] = imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_LCD_CLK] = imx_clk_scu("lcd_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER, clk_cells);
/* DMA SS */
imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER);
imx_clk_scu("uart4_clk", IMX_SC_R_UART_4, IMX_SC_PM_CLK_PER);
imx_clk_scu("sim0_clk", IMX_SC_R_EMVSIM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("spi0_clk", IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("spi1_clk", IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("spi2_clk", IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("spi3_clk", IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER);
imx_clk_scu("can0_clk", IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("can1_clk", IMX_SC_R_CAN_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("can2_clk", IMX_SC_R_CAN_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("i2c0_clk", IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("i2c1_clk", IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("i2c2_clk", IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("i2c3_clk", IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER);
imx_clk_scu("i2c4_clk", IMX_SC_R_I2C_4, IMX_SC_PM_CLK_PER);
imx_clk_scu("ftm0_clk", IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("ftm1_clk", IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("adc1_clk", IMX_SC_R_ADC_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu2("lcd_clk", lcd_sels, ARRAY_SIZE(lcd_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER);
imx_clk_scu2("lcd_pxl_clk", lcd_pxl_sels, ARRAY_SIZE(lcd_pxl_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_MISC0);
imx_clk_scu("lcd_pxl_bypass_div_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("elcdif_pll", IMX_SC_R_ELCDIF_PLL, IMX_SC_PM_CLK_PLL);
/* Audio SS */
imx_clk_scu("audio_pll0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_PLL);
imx_clk_scu("audio_pll1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_PLL);
imx_clk_scu("audio_pll_div_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC0);
imx_clk_scu("audio_pll_div_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC0);
imx_clk_scu("audio_rec_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC1);
imx_clk_scu("audio_rec_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC1);
/* Connectivity */
clks[IMX_CONN_SDHC0_CLK] = imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CONN_SDHC1_CLK] = imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CONN_SDHC2_CLK] = imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CONN_ENET0_ROOT_CLK] = imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CONN_ENET0_BYPASS_CLK] = imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
clks[IMX_CONN_ENET0_RGMII_CLK] = imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0, clk_cells);
clks[IMX_CONN_ENET1_ROOT_CLK] = imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CONN_ENET1_BYPASS_CLK] = imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
clks[IMX_CONN_ENET1_RGMII_CLK] = imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0, clk_cells);
clks[IMX_CONN_GPMI_BCH_IO_CLK] = imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS, clk_cells);
clks[IMX_CONN_GPMI_BCH_CLK] = imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CONN_USB2_ACLK] = imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CONN_USB2_BUS_CLK] = imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS, clk_cells);
clks[IMX_CONN_USB2_LPM_CLK] = imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC, clk_cells);
imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
imx_clk_divider_gpr_scu("enet0_ref_div", "enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_C_CLKDIV);
imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK);
imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);
imx_clk_gate_gpr_scu("enet0_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, true);
imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV);
imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK);
imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);
imx_clk_gate_gpr_scu("enet1_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, true);
imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);
imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);
imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS);
imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC);
/* Display controller SS */
clks[IMX_DC0_DISP0_CLK] = imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
clks[IMX_DC0_DISP1_CLK] = imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
clks[IMX_DC0_PLL0_CLK] = imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
clks[IMX_DC0_PLL1_CLK] = imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
clks[IMX_DC0_BYPASS0_CLK] = imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells);
clks[IMX_DC0_BYPASS1_CLK] = imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells);
imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0);
imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1);
imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL);
imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL);
imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu2("dc1_disp0_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0);
imx_clk_scu2("dc1_disp1_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC1);
imx_clk_scu("dc1_pll0_clk", IMX_SC_R_DC_1_PLL_0, IMX_SC_PM_CLK_PLL);
imx_clk_scu("dc1_pll1_clk", IMX_SC_R_DC_1_PLL_1, IMX_SC_PM_CLK_PLL);
imx_clk_scu("dc1_bypass0_clk", IMX_SC_R_DC_1_VIDEO0, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("dc1_bypass1_clk", IMX_SC_R_DC_1_VIDEO1, IMX_SC_PM_CLK_BYPASS);
/* MIPI-LVDS SS */
clks[IMX_MIPI0_LVDS_PIXEL_CLK] = imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI0_LVDS_BYPASS_CLK] = imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
clks[IMX_MIPI0_LVDS_PHY_CLK] = imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3, clk_cells);
clks[IMX_MIPI0_I2C0_CLK] = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI0_I2C1_CLK] = imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI0_PWM0_CLK] = imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_MIPI1_LVDS_PIXEL_CLK] = imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI1_LVDS_BYPASS_CLK] = imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
clks[IMX_MIPI1_LVDS_PHY_CLK] = imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3, clk_cells);
clks[IMX_MIPI1_I2C0_CLK] = imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI1_I2C1_CLK] = imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI1_PWM0_CLK] = imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);
imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS);
imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS);
imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY);
imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);
imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS);
imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS);
imx_clk_scu2("mipi1_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY);
imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("lvds0_i2c0_clk", IMX_SC_R_LVDS_0_I2C_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("lvds0_i2c1_clk", IMX_SC_R_LVDS_0_I2C_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("lvds0_pwm0_clk", IMX_SC_R_LVDS_0_PWM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("lvds1_i2c0_clk", IMX_SC_R_LVDS_1_I2C_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("lvds1_i2c1_clk", IMX_SC_R_LVDS_1_I2C_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("lvds1_pwm0_clk", IMX_SC_R_LVDS_1_PWM_0, IMX_SC_PM_CLK_PER);
/* MIPI CSI SS */
clks[IMX_CSI0_CORE_CLK] = imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CSI0_ESC_CLK] = imx_clk_scu("mipi_csi0_esc_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC, clk_cells);
clks[IMX_CSI0_I2C0_CLK] = imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CSI0_PWM0_CLK] = imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi_csi0_esc_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC);
imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi_csi1_core_clk", IMX_SC_R_CSI_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi_csi1_esc_clk", IMX_SC_R_CSI_1, IMX_SC_PM_CLK_MISC);
imx_clk_scu("mipi_csi1_i2c0_clk", IMX_SC_R_CSI_1_I2C_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi_csi1_pwm0_clk", IMX_SC_R_CSI_1_PWM_0, IMX_SC_PM_CLK_PER);
/* Parallel Interface SS */
imx_clk_scu("pi_dpll_clk", IMX_SC_R_PI_0_PLL, IMX_SC_PM_CLK_PLL);
imx_clk_scu2("pi_per_div_clk", pi_pll0_sels, ARRAY_SIZE(pi_pll0_sels), IMX_SC_R_PI_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("pi_mclk_div_clk", IMX_SC_R_PI_0, IMX_SC_PM_CLK_MISC0);
imx_clk_scu("pi_i2c0_div_clk", IMX_SC_R_PI_0_I2C_0, IMX_SC_PM_CLK_PER);
/* GPU SS */
clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC, clk_cells);
imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);
for (i = 0; i < clk_data->num; i++) {
if (IS_ERR(clks[i]))
pr_warn("i.MX clk %u: register failed with %ld\n",
i, PTR_ERR(clks[i]));
}
imx_clk_scu("gpu_core1_clk", IMX_SC_R_GPU_1_PID0, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpu_shader1_clk", IMX_SC_R_GPU_1_PID0, IMX_SC_PM_CLK_MISC);
if (clk_cells == 2) {
ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks);
if (ret)
imx_clk_scu_unregister();
} else {
/*
* legacy binding code path doesn't unregister here because
* it will be removed later.
*/
ret = of_clk_add_hw_provider(ccm_node, of_clk_hw_onecell_get, clk_data);
}
/* CM40 SS */
imx_clk_scu("cm40_i2c_div", IMX_SC_R_M4_0_I2C, IMX_SC_PM_CLK_PER);
imx_clk_scu("cm40_lpuart_div", IMX_SC_R_M4_0_UART, IMX_SC_PM_CLK_PER);
/* CM41 SS */
imx_clk_scu("cm41_i2c_div", IMX_SC_R_M4_1_I2C, IMX_SC_PM_CLK_PER);
/* HDMI TX SS */
imx_clk_scu("hdmi_dig_pll_clk", IMX_SC_R_HDMI_PLL_0, IMX_SC_PM_CLK_PLL);
imx_clk_scu("hdmi_av_pll_clk", IMX_SC_R_HDMI_PLL_1, IMX_SC_PM_CLK_PLL);
imx_clk_scu2("hdmi_pixel_mux_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC0);
imx_clk_scu2("hdmi_pixel_link_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC1);
imx_clk_scu("hdmi_ipg_clk", IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC4);
imx_clk_scu("hdmi_i2c0_clk", IMX_SC_R_HDMI_I2C_0, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("hdmi_hdp_core_clk", IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC2);
imx_clk_scu2("hdmi_pxl_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC3);
imx_clk_scu("hdmi_i2s_bypass_clk", IMX_SC_R_HDMI_I2S, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("hdmi_i2s_clk", IMX_SC_R_HDMI_I2S, IMX_SC_PM_CLK_MISC0);
/* HDMI RX SS */
imx_clk_scu("hdmi_rx_i2s_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC0);
imx_clk_scu("hdmi_rx_spdif_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC1);
imx_clk_scu("hdmi_rx_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("hdmi_rx_i2c0_clk", IMX_SC_R_HDMI_RX_I2C_0, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("hdmi_rx_pwm_clk", IMX_SC_R_HDMI_RX_PWM_0, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("hdmi_rx_spdif_clk", IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC0);
imx_clk_scu2("hdmi_rx_hd_ref_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC1);
imx_clk_scu2("hdmi_rx_hd_core_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC2);
imx_clk_scu2("hdmi_rx_pxl_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC3);
imx_clk_scu("hdmi_rx_i2s_clk", IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC4);
ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks);
if (ret)
imx_clk_scu_unregister();
return ret;
}
static const struct of_device_id imx8qxp_match[] = {
{ .compatible = "fsl,scu-clk", },
{ .compatible = "fsl,imx8qxp-clk", },
{ .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, },
{ .compatible = "fsl,imx8qm-clk", &imx_clk_scu_rsrc_imx8qm, },
{ /* sentinel */ }
};

310
drivers/clk/imx/clk-scu.c
View File

@ -1,11 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
* Copyright 2018-2021 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/firmware/imx/rsrc.h>
#include <linux/arm-smccc.h>
#include <linux/bsearch.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/of_platform.h>
@ -22,6 +23,7 @@
static struct imx_sc_ipc *ccm_ipc_handle;
static struct device_node *pd_np;
static struct platform_driver imx_clk_scu_driver;
static const struct imx_clk_scu_rsrc_table *rsrc_table;
struct imx_scu_clk_node {
const char *name;
@ -48,10 +50,28 @@ struct clk_scu {
u8 clk_type;
/* for state save&restore */
struct clk_hw *parent;
u8 parent_index;
bool is_enabled;
u32 rate;
};
/*
* struct clk_gpr_scu - Description of one SCU GPR clock
* @hw: the common clk_hw
* @rsrc_id: resource ID of this SCU clock
* @gpr_id: GPR ID index to control the divider
*/
struct clk_gpr_scu {
struct clk_hw hw;
u16 rsrc_id;
u8 gpr_id;
u8 flags;
bool gate_invert;
};
#define to_clk_gpr_scu(_hw) container_of(_hw, struct clk_gpr_scu, hw)
/*
* struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
* @hdr: SCU protocol header
@ -151,7 +171,26 @@ static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
return container_of(hw, struct clk_scu, hw);
}
int imx_clk_scu_init(struct device_node *np)
static inline int imx_scu_clk_search_cmp(const void *rsrc, const void *rsrc_p)
{
return *(u32 *)rsrc - *(u32 *)rsrc_p;
}
static bool imx_scu_clk_is_valid(u32 rsrc_id)
{
void *p;
if (!rsrc_table)
return true;
p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num,
sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp);
return p != NULL;
}
int imx_clk_scu_init(struct device_node *np,
const struct imx_clk_scu_rsrc_table *data)
{
u32 clk_cells;
int ret, i;
@ -170,6 +209,8 @@ int imx_clk_scu_init(struct device_node *np)
pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd");
if (!pd_np)
return -EINVAL;
rsrc_table = data;
}
return platform_driver_register(&imx_clk_scu_driver);
@ -234,8 +275,10 @@ static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate,
struct arm_smccc_res res;
unsigned long cluster_id;
if (clk->rsrc_id == IMX_SC_R_A35)
if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53)
cluster_id = 0;
else if (clk->rsrc_id == IMX_SC_R_A72)
cluster_id = 1;
else
return -EINVAL;
@ -296,6 +339,8 @@ static u8 clk_scu_get_parent(struct clk_hw *hw)
return 0;
}
clk->parent_index = msg.data.resp.parent;
return msg.data.resp.parent;
}
@ -304,6 +349,7 @@ static int clk_scu_set_parent(struct clk_hw *hw, u8 index)
struct clk_scu *clk = to_clk_scu(hw);
struct imx_sc_msg_set_clock_parent msg;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
int ret;
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_PM;
@ -314,7 +360,16 @@ static int clk_scu_set_parent(struct clk_hw *hw, u8 index)
msg.clk = clk->clk_type;
msg.parent = index;
return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
if (ret) {
pr_err("%s: failed to set clock parent %d\n",
clk_hw_get_name(hw), ret);
return ret;
}
clk->parent_index = index;
return 0;
}
static int sc_pm_clock_enable(struct imx_sc_ipc *ipc, u16 resource,
@ -386,6 +441,12 @@ static const struct clk_ops clk_scu_cpu_ops = {
.unprepare = clk_scu_unprepare,
};
static const struct clk_ops clk_scu_pi_ops = {
.recalc_rate = clk_scu_recalc_rate,
.round_rate = clk_scu_round_rate,
.set_rate = clk_scu_set_rate,
};
struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
const char * const *parents, int num_parents,
u32 rsrc_id, u8 clk_type)
@ -404,8 +465,10 @@ struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
init.name = name;
init.ops = &clk_scu_ops;
if (rsrc_id == IMX_SC_R_A35)
if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53 || rsrc_id == IMX_SC_R_A72)
init.ops = &clk_scu_cpu_ops;
else if (rsrc_id == IMX_SC_R_PI_0_PLL)
init.ops = &clk_scu_pi_ops;
else
init.ops = &clk_scu_ops;
init.parent_names = parents;
@ -458,15 +521,19 @@ static int imx_clk_scu_probe(struct platform_device *pdev)
struct clk_hw *hw;
int ret;
pm_runtime_set_suspended(dev);
pm_runtime_set_autosuspend_delay(dev, 50);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_enable(dev);
if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||
(clk->rsrc == IMX_SC_R_A72))) {
pm_runtime_set_suspended(dev);
pm_runtime_set_autosuspend_delay(dev, 50);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
if (ret) {
pm_runtime_disable(dev);
return ret;
ret = pm_runtime_get_sync(dev);
if (ret) {
pm_genpd_remove_device(dev);
pm_runtime_disable(dev);
return ret;
}
}
hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents,
@ -479,8 +546,11 @@ static int imx_clk_scu_probe(struct platform_device *pdev)
clk->hw = hw;
list_add_tail(&clk->node, &imx_scu_clks[clk->rsrc]);
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||
(clk->rsrc == IMX_SC_R_A72))) {
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
}
dev_dbg(dev, "register SCU clock rsrc:%d type:%d\n", clk->rsrc,
clk->clk_type);
@ -491,10 +561,28 @@ static int imx_clk_scu_probe(struct platform_device *pdev)
static int __maybe_unused imx_clk_scu_suspend(struct device *dev)
{
struct clk_scu *clk = dev_get_drvdata(dev);
u32 rsrc_id = clk->rsrc_id;
clk->rate = clk_hw_get_rate(&clk->hw);
if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) ||
(rsrc_id == IMX_SC_R_A72))
return 0;
clk->parent = clk_hw_get_parent(&clk->hw);
/* DC SS needs to handle bypass clock using non-cached clock rate */
if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 ||
clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 ||
clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 ||
clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1)
clk->rate = clk_scu_recalc_rate(&clk->hw, 0);
else
clk->rate = clk_hw_get_rate(&clk->hw);
clk->is_enabled = clk_hw_is_enabled(&clk->hw);
if (clk->parent)
dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent),
clk->parent_index);
if (clk->rate)
dev_dbg(dev, "save rate %d\n", clk->rate);
@ -507,15 +595,27 @@ static int __maybe_unused imx_clk_scu_suspend(struct device *dev)
static int __maybe_unused imx_clk_scu_resume(struct device *dev)
{
struct clk_scu *clk = dev_get_drvdata(dev);
u32 rsrc_id = clk->rsrc_id;
int ret = 0;
if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) ||
(rsrc_id == IMX_SC_R_A72))
return 0;
if (clk->parent) {
ret = clk_scu_set_parent(&clk->hw, clk->parent_index);
dev_dbg(dev, "restore parent %s idx %u %s\n",
clk_hw_get_name(clk->parent),
clk->parent_index, !ret ? "success" : "failed");
}
if (clk->rate) {
ret = clk_scu_set_rate(&clk->hw, clk->rate, 0);
dev_dbg(dev, "restore rate %d %s\n", clk->rate,
!ret ? "success" : "failed");
}
if (clk->is_enabled) {
if (clk->is_enabled && rsrc_id != IMX_SC_R_PI_0_PLL) {
ret = clk_scu_prepare(&clk->hw);
dev_dbg(dev, "restore enabled state %s\n",
!ret ? "success" : "failed");
@ -567,6 +667,9 @@ struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
struct platform_device *pdev;
int ret;
if (!imx_scu_clk_is_valid(rsrc_id))
return ERR_PTR(-EINVAL);
pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE);
if (!pdev) {
pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n",
@ -605,3 +708,176 @@ void imx_clk_scu_unregister(void)
}
}
}
static unsigned long clk_gpr_div_scu_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
unsigned long rate = 0;
u32 val;
int err;
err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
clk->gpr_id, &val);
rate = val ? parent_rate / 2 : parent_rate;
return err ? 0 : rate;
}
static long clk_gpr_div_scu_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
if (rate < *prate)
rate = *prate / 2;
else
rate = *prate;
return rate;
}
static int clk_gpr_div_scu_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
uint32_t val;
int err;
val = (rate < parent_rate) ? 1 : 0;
err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
clk->gpr_id, val);
return err ? -EINVAL : 0;
}
static const struct clk_ops clk_gpr_div_scu_ops = {
.recalc_rate = clk_gpr_div_scu_recalc_rate,
.round_rate = clk_gpr_div_scu_round_rate,
.set_rate = clk_gpr_div_scu_set_rate,
};
static u8 clk_gpr_mux_scu_get_parent(struct clk_hw *hw)
{
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
u32 val = 0;
imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
clk->gpr_id, &val);
return (u8)val;
}
static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
clk->gpr_id, index);
}
static const struct clk_ops clk_gpr_mux_scu_ops = {
.get_parent = clk_gpr_mux_scu_get_parent,
.set_parent = clk_gpr_mux_scu_set_parent,
};
static int clk_gpr_gate_scu_prepare(struct clk_hw *hw)
{
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
clk->gpr_id, !clk->gate_invert);
}
static void clk_gpr_gate_scu_unprepare(struct clk_hw *hw)
{
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
int ret;
ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
clk->gpr_id, clk->gate_invert);
if (ret)
pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
ret);
}
static int clk_gpr_gate_scu_is_prepared(struct clk_hw *hw)
{
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
int ret;
u32 val;
ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
clk->gpr_id, &val);
if (ret)
return ret;
return clk->gate_invert ? !val : val;
}
static const struct clk_ops clk_gpr_gate_scu_ops = {
.prepare = clk_gpr_gate_scu_prepare,
.unprepare = clk_gpr_gate_scu_unprepare,
.is_prepared = clk_gpr_gate_scu_is_prepared,
};
struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
bool invert)
{
struct imx_scu_clk_node *clk_node;
struct clk_gpr_scu *clk;
struct clk_hw *hw;
struct clk_init_data init;
int ret;
if (rsrc_id >= IMX_SC_R_LAST || gpr_id >= IMX_SC_C_LAST)
return ERR_PTR(-EINVAL);
clk_node = kzalloc(sizeof(*clk_node), GFP_KERNEL);
if (!clk_node)
return ERR_PTR(-ENOMEM);
if (!imx_scu_clk_is_valid(rsrc_id))
return ERR_PTR(-EINVAL);
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
if (!clk) {
kfree(clk_node);
return ERR_PTR(-ENOMEM);
}
clk->rsrc_id = rsrc_id;
clk->gpr_id = gpr_id;
clk->flags = flags;
clk->gate_invert = invert;
if (flags & IMX_SCU_GPR_CLK_GATE)
init.ops = &clk_gpr_gate_scu_ops;
if (flags & IMX_SCU_GPR_CLK_DIV)
init.ops = &clk_gpr_div_scu_ops;
if (flags & IMX_SCU_GPR_CLK_MUX)
init.ops = &clk_gpr_mux_scu_ops;
init.flags = 0;
init.name = name;
init.parent_names = parent_name;
init.num_parents = num_parents;
clk->hw.init = &init;
hw = &clk->hw;
ret = clk_hw_register(NULL, hw);
if (ret) {
kfree(clk);
kfree(clk_node);
hw = ERR_PTR(ret);
} else {
clk_node->hw = hw;
clk_node->clk_type = gpr_id;
list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]);
}
return hw;
}

56
drivers/clk/imx/clk-scu.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
* Copyright 2018-2021 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
@ -10,10 +10,22 @@
#include <linux/firmware/imx/sci.h>
#include <linux/of.h>
#define IMX_SCU_GPR_CLK_GATE BIT(0)
#define IMX_SCU_GPR_CLK_DIV BIT(1)
#define IMX_SCU_GPR_CLK_MUX BIT(2)
struct imx_clk_scu_rsrc_table {
const u32 *rsrc;
u8 num;
};
extern struct list_head imx_scu_clks[];
extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm;
int imx_clk_scu_init(struct device_node *np);
int imx_clk_scu_init(struct device_node *np,
const struct imx_clk_scu_rsrc_table *data);
struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec,
void *data);
struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
@ -31,23 +43,20 @@ struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
void __iomem *reg, u8 bit_idx, bool hw_gate);
void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
bool invert);
static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
u8 clk_type, u8 clk_cells)
u8 clk_type)
{
if (clk_cells == 2)
return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
else
return __imx_clk_scu(NULL, name, NULL, 0, rsrc_id, clk_type);
return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
}
static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents,
int num_parents, u32 rsrc_id, u8 clk_type,
u8 clk_cells)
int num_parents, u32 rsrc_id, u8 clk_type)
{
if (clk_cells == 2)
return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
else
return __imx_clk_scu(NULL, name, parents, num_parents, rsrc_id, clk_type);
return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
}
static inline struct clk_hw *imx_clk_lpcg_scu_dev(struct device *dev, const char *name,
@ -65,4 +74,25 @@ static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *pare
return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg,
bit_idx, hw_gate);
}
static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name,
u32 rsrc_id, u8 gpr_id, bool invert)
{
return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
IMX_SCU_GPR_CLK_GATE, invert);
}
static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name,
u32 rsrc_id, u8 gpr_id)
{
return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
IMX_SCU_GPR_CLK_DIV, 0);
}
static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names,
int num_parents, u32 rsrc_id, u8 gpr_id)
{
return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id,
gpr_id, IMX_SCU_GPR_CLK_MUX, 0);
}
#endif

10
drivers/clk/ingenic/Kconfig
View File

@ -25,6 +25,16 @@ config INGENIC_CGU_JZ4725B
If building for a JZ4725B SoC, you want to say Y here.
config INGENIC_CGU_JZ4760
bool "Ingenic JZ4760 CGU driver"
default MACH_JZ4760
select INGENIC_CGU_COMMON
help
Support the clocks provided by the CGU hardware on Ingenic JZ4760
and compatible SoCs.
If building for a JZ4760 SoC, you want to say Y here.
config INGENIC_CGU_JZ4770
bool "Ingenic JZ4770 CGU driver"
default MACH_JZ4770

1
drivers/clk/ingenic/Makefile
View File

@ -2,6 +2,7 @@
obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o
obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o

92
drivers/clk/ingenic/cgu.c
View File

@ -99,13 +99,14 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
od_enc = ctl >> pll_info->od_shift;
od_enc &= GENMASK(pll_info->od_bits - 1, 0);
ctl = readl(cgu->base + pll_info->bypass_reg);
if (pll_info->bypass_bit >= 0) {
ctl = readl(cgu->base + pll_info->bypass_reg);
bypass = !pll_info->no_bypass_bit &&
!!(ctl & BIT(pll_info->bypass_bit));
bypass = !!(ctl & BIT(pll_info->bypass_bit));
if (bypass)
return parent_rate;
if (bypass)
return parent_rate;
}
for (od = 0; od < pll_info->od_max; od++) {
if (pll_info->od_encoding[od] == od_enc)
@ -118,28 +119,42 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
n * od);
}
static unsigned long
ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info,
unsigned long rate, unsigned long parent_rate,
unsigned *pm, unsigned *pn, unsigned *pod)
static void
ingenic_pll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,
unsigned long rate, unsigned long parent_rate,
unsigned int *pm, unsigned int *pn, unsigned int *pod)
{
const struct ingenic_cgu_pll_info *pll_info;
unsigned m, n, od;
pll_info = &clk_info->pll;
od = 1;
unsigned int m, n, od = 1;
/*
* The frequency after the input divider must be between 10 and 50 MHz.
* The highest divider yields the best resolution.
*/
n = parent_rate / (10 * MHZ);
n = min_t(unsigned, n, 1 << clk_info->pll.n_bits);
n = max_t(unsigned, n, pll_info->n_offset);
n = min_t(unsigned int, n, 1 << pll_info->n_bits);
n = max_t(unsigned int, n, pll_info->n_offset);
m = (rate / MHZ) * od * n / (parent_rate / MHZ);
m = min_t(unsigned, m, 1 << clk_info->pll.m_bits);
m = max_t(unsigned, m, pll_info->m_offset);
m = min_t(unsigned int, m, 1 << pll_info->m_bits);
m = max_t(unsigned int, m, pll_info->m_offset);
*pm = m;
*pn = n;
*pod = od;
}
static unsigned long
ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info,
unsigned long rate, unsigned long parent_rate,
unsigned int *pm, unsigned int *pn, unsigned int *pod)
{
const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
unsigned int m, n, od;
if (pll_info->calc_m_n_od)
(*pll_info->calc_m_n_od)(pll_info, rate, parent_rate, &m, &n, &od);
else
ingenic_pll_calc_m_n_od(pll_info, rate, parent_rate, &m, &n, &od);
if (pm)
*pm = m;
@ -225,11 +240,13 @@ static int ingenic_pll_enable(struct clk_hw *hw)
u32 ctl;
spin_lock_irqsave(&cgu->lock, flags);
ctl = readl(cgu->base + pll_info->bypass_reg);
if (pll_info->bypass_bit >= 0) {
ctl = readl(cgu->base + pll_info->bypass_reg);
ctl &= ~BIT(pll_info->bypass_bit);
ctl &= ~BIT(pll_info->bypass_bit);
writel(ctl, cgu->base + pll_info->bypass_reg);
writel(ctl, cgu->base + pll_info->bypass_reg);
}
ctl = readl(cgu->base + pll_info->reg);
@ -369,18 +386,23 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
struct ingenic_cgu *cgu = ingenic_clk->cgu;
unsigned long rate = parent_rate;
u32 div_reg, div;
u8 parent;
if (clk_info->type & CGU_CLK_DIV) {
div_reg = readl(cgu->base + clk_info->div.reg);
div = (div_reg >> clk_info->div.shift) &
GENMASK(clk_info->div.bits - 1, 0);
parent = ingenic_clk_get_parent(hw);
if (clk_info->div.div_table)
div = clk_info->div.div_table[div];
else
div = (div + 1) * clk_info->div.div;
if (!(clk_info->div.bypass_mask & BIT(parent))) {
div_reg = readl(cgu->base + clk_info->div.reg);
div = (div_reg >> clk_info->div.shift) &
GENMASK(clk_info->div.bits - 1, 0);
rate /= div;
if (clk_info->div.div_table)
div = clk_info->div.div_table[div];
else
div = (div + 1) * clk_info->div.div;
rate /= div;
}
} else if (clk_info->type & CGU_CLK_FIXDIV) {
rate /= clk_info->fixdiv.div;
}
@ -410,10 +432,16 @@ ingenic_clk_calc_hw_div(const struct ingenic_cgu_clk_info *clk_info,
}
static unsigned
ingenic_clk_calc_div(const struct ingenic_cgu_clk_info *clk_info,
ingenic_clk_calc_div(struct clk_hw *hw,
const struct ingenic_cgu_clk_info *clk_info,
unsigned long parent_rate, unsigned long req_rate)
{
unsigned int div, hw_div;
u8 parent;
parent = ingenic_clk_get_parent(hw);
if (clk_info->div.bypass_mask & BIT(parent))
return 1;
/* calculate the divide */
div = DIV_ROUND_UP(parent_rate, req_rate);
@ -448,7 +476,7 @@ ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate,
unsigned int div = 1;
if (clk_info->type & CGU_CLK_DIV)
div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);
div = ingenic_clk_calc_div(hw, clk_info, *parent_rate, req_rate);
else if (clk_info->type & CGU_CLK_FIXDIV)
div = clk_info->fixdiv.div;
else if (clk_hw_can_set_rate_parent(hw))
@ -480,7 +508,7 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
int ret = 0;
if (clk_info->type & CGU_CLK_DIV) {
div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate);
div = ingenic_clk_calc_div(hw, clk_info, parent_rate, req_rate);
rate = DIV_ROUND_UP(parent_rate, div);
if (rate != req_rate)

12
drivers/clk/ingenic/cgu.h
View File

@ -39,10 +39,10 @@
* their encoded values in the PLL control register, or -1 for
* unsupported values
* @bypass_reg: the offset of the bypass control register within the CGU
* @bypass_bit: the index of the bypass bit in the PLL control register
* @bypass_bit: the index of the bypass bit in the PLL control register, or
* -1 if there is no bypass bit
* @enable_bit: the index of the enable bit in the PLL control register
* @stable_bit: the index of the stable bit in the PLL control register
* @no_bypass_bit: if set, the PLL has no bypass functionality
*/
struct ingenic_cgu_pll_info {
unsigned reg;
@ -52,10 +52,12 @@ struct ingenic_cgu_pll_info {
u8 n_shift, n_bits, n_offset;
u8 od_shift, od_bits, od_max;
unsigned bypass_reg;
u8 bypass_bit;
s8 bypass_bit;
u8 enable_bit;
u8 stable_bit;
bool no_bypass_bit;
void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info,
unsigned long rate, unsigned long parent_rate,
unsigned int *m, unsigned int *n, unsigned int *od);
};
/**
@ -84,6 +86,7 @@ struct ingenic_cgu_mux_info {
* isn't one
* @busy_bit: the index of the busy bit within reg, or -1 if there isn't one
* @stop_bit: the index of the stop bit within reg, or -1 if there isn't one
* @bypass_mask: mask of parent clocks for which the divider does not apply
* @div_table: optional table to map the value read from the register to the
* actual divider value
*/
@ -95,6 +98,7 @@ struct ingenic_cgu_div_info {
s8 ce_bit;
s8 busy_bit;
s8 stop_bit;
u8 bypass_mask;
const u8 *div_table;
};

12
drivers/clk/ingenic/jz4725b-cgu.c
View File

@ -80,7 +80,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
"pll half", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = {
CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
jz4725b_cgu_pll_half_div_table,
},
},
@ -89,7 +89,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
"cclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = {
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
jz4725b_cgu_cpccr_div_table,
},
},
@ -98,7 +98,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
"hclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = {
CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
jz4725b_cgu_cpccr_div_table,
},
},
@ -107,7 +107,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
"pclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = {
CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
jz4725b_cgu_cpccr_div_table,
},
},
@ -116,7 +116,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
"mclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = {
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
jz4725b_cgu_cpccr_div_table,
},
},
@ -125,7 +125,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
"ipu", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = {
CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
jz4725b_cgu_cpccr_div_table,
},
.gate = { CGU_REG_CLKGR, 13 },

12
drivers/clk/ingenic/jz4740-cgu.c
View File

@ -95,7 +95,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
"pll half", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
.div = {
CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
jz4740_cgu_pll_half_div_table,
},
},
@ -104,7 +104,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
"cclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
.div = {
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
jz4740_cgu_cpccr_div_table,
},
},
@ -113,7 +113,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
"hclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
.div = {
CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
jz4740_cgu_cpccr_div_table,
},
},
@ -122,7 +122,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
"pclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
.div = {
CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
jz4740_cgu_cpccr_div_table,
},
},
@ -131,7 +131,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
"mclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
.div = {
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
jz4740_cgu_cpccr_div_table,
},
},
@ -140,7 +140,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
.div = {
CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1,
CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1, 0,
jz4740_cgu_cpccr_div_table,
},
.gate = { CGU_REG_CLKGR, 10 },

428
drivers/clk/ingenic/jz4760-cgu.c Normal file
View File

@ -0,0 +1,428 @@
// SPDX-License-Identifier: GPL-2.0
/*
* JZ4760 SoC CGU driver
* Copyright 2018, Paul Cercueil <paul@crapouillou.net>
*/
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <dt-bindings/clock/jz4760-cgu.h>
#include "cgu.h"
#include "pm.h"
#define MHZ (1000 * 1000)
/*
* CPM registers offset address definition
*/
#define CGU_REG_CPCCR 0x00
#define CGU_REG_LCR 0x04
#define CGU_REG_CPPCR0 0x10
#define CGU_REG_CLKGR0 0x20
#define CGU_REG_OPCR 0x24
#define CGU_REG_CLKGR1 0x28
#define CGU_REG_CPPCR1 0x30
#define CGU_REG_USBPCR 0x3c
#define CGU_REG_USBCDR 0x50
#define CGU_REG_I2SCDR 0x60
#define CGU_REG_LPCDR 0x64
#define CGU_REG_MSCCDR 0x68
#define CGU_REG_UHCCDR 0x6c
#define CGU_REG_SSICDR 0x74
#define CGU_REG_CIMCDR 0x7c
#define CGU_REG_GPSCDR 0x80
#define CGU_REG_PCMCDR 0x84
#define CGU_REG_GPUCDR 0x88
static const s8 pll_od_encoding[8] = {
0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
};
static const u8 jz4760_cgu_cpccr_div_table[] = {
1, 2, 3, 4, 6, 8,
};
static const u8 jz4760_cgu_pll_half_div_table[] = {
2, 1,
};
static void
jz4760_cgu_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,
unsigned long rate, unsigned long parent_rate,
unsigned int *pm, unsigned int *pn, unsigned int *pod)
{
unsigned int m, n, od, m_max = (1 << pll_info->m_bits) - 2;
/* The frequency after the N divider must be between 1 and 50 MHz. */
n = parent_rate / (1 * MHZ);
/* The N divider must be >= 2. */
n = clamp_val(n, 2, 1 << pll_info->n_bits);
for (;; n >>= 1) {
od = (unsigned int)-1;
do {
m = (rate / MHZ) * (1 << ++od) * n / (parent_rate / MHZ);
} while ((m > m_max || m & 1) && (od < 4));
if (od < 4 && m >= 4 && m <= m_max)
break;
}
*pm = m;
*pn = n;
*pod = 1 << od;
}
static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = {
/* External clocks */
[JZ4760_CLK_EXT] = { "ext", CGU_CLK_EXT },
[JZ4760_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
/* PLLs */
[JZ4760_CLK_PLL0] = {
"pll0", CGU_CLK_PLL,
.parents = { JZ4760_CLK_EXT },
.pll = {
.reg = CGU_REG_CPPCR0,
.rate_multiplier = 1,
.m_shift = 23,
.m_bits = 8,
.m_offset = 0,
.n_shift = 18,
.n_bits = 4,
.n_offset = 0,
.od_shift = 16,
.od_bits = 2,
.od_max = 8,
.od_encoding = pll_od_encoding,
.bypass_reg = CGU_REG_CPPCR0,
.bypass_bit = 9,
.enable_bit = 8,
.stable_bit = 10,
.calc_m_n_od = jz4760_cgu_calc_m_n_od,
},
},
[JZ4760_CLK_PLL1] = {
/* TODO: PLL1 can depend on PLL0 */
"pll1", CGU_CLK_PLL,
.parents = { JZ4760_CLK_EXT },
.pll = {
.reg = CGU_REG_CPPCR1,
.rate_multiplier = 1,
.m_shift = 23,
.m_bits = 8,
.m_offset = 0,
.n_shift = 18,
.n_bits = 4,
.n_offset = 0,
.od_shift = 16,
.od_bits = 2,
.od_max = 8,
.od_encoding = pll_od_encoding,
.bypass_bit = -1,
.enable_bit = 7,
.stable_bit = 6,
.calc_m_n_od = jz4760_cgu_calc_m_n_od,
},
},
/* Main clocks */
[JZ4760_CLK_CCLK] = {
"cclk", CGU_CLK_DIV,
.parents = { JZ4760_CLK_PLL0, },
.div = {
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
jz4760_cgu_cpccr_div_table,
},
},
[JZ4760_CLK_HCLK] = {
"hclk", CGU_CLK_DIV,
.parents = { JZ4760_CLK_PLL0, },
.div = {
CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
jz4760_cgu_cpccr_div_table,
},
},
[JZ4760_CLK_SCLK] = {
"sclk", CGU_CLK_DIV,
.parents = { JZ4760_CLK_PLL0, },
.div = {
CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0,
jz4760_cgu_cpccr_div_table,
},
},
[JZ4760_CLK_H2CLK] = {
"h2clk", CGU_CLK_DIV,
.parents = { JZ4760_CLK_PLL0, },
.div = {
CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
jz4760_cgu_cpccr_div_table,
},
},
[JZ4760_CLK_MCLK] = {
"mclk", CGU_CLK_DIV,
.parents = { JZ4760_CLK_PLL0, },
.div = {
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
jz4760_cgu_cpccr_div_table,
},
},
[JZ4760_CLK_PCLK] = {
"pclk", CGU_CLK_DIV,
.parents = { JZ4760_CLK_PLL0, },
.div = {
CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
jz4760_cgu_cpccr_div_table,
},
},
/* Divided clocks */
[JZ4760_CLK_PLL0_HALF] = {
"pll0_half", CGU_CLK_DIV,
.parents = { JZ4760_CLK_PLL0 },
.div = {
CGU_REG_CPCCR, 21, 1, 1, 22, -1, -1, 0,
jz4760_cgu_pll_half_div_table,
},
},
/* Those divided clocks can connect to PLL0 or PLL1 */
[JZ4760_CLK_UHC] = {
"uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
.mux = { CGU_REG_UHCCDR, 31, 1 },
.div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
.gate = { CGU_REG_CLKGR0, 24 },
},
[JZ4760_CLK_GPU] = {
"gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
.mux = { CGU_REG_GPUCDR, 31, 1 },
.div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 },
.gate = { CGU_REG_CLKGR1, 9 },
},
[JZ4760_CLK_LPCLK_DIV] = {
"lpclk_div", CGU_CLK_DIV | CGU_CLK_MUX,
.parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
.mux = { CGU_REG_LPCDR, 29, 1 },
.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
},
[JZ4760_CLK_TVE] = {
"tve", CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_EXT, },
.mux = { CGU_REG_LPCDR, 31, 1 },
.gate = { CGU_REG_CLKGR0, 27 },
},
[JZ4760_CLK_LPCLK] = {
"lpclk", CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_TVE, },
.mux = { CGU_REG_LPCDR, 30, 1 },
.gate = { CGU_REG_CLKGR0, 28 },
},
[JZ4760_CLK_GPS] = {
"gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
.mux = { CGU_REG_GPSCDR, 31, 1 },
.div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 },
.gate = { CGU_REG_CLKGR0, 22 },
},
/* Those divided clocks can connect to EXT, PLL0 or PLL1 */
[JZ4760_CLK_PCM] = {
"pcm", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4760_CLK_EXT, -1,
JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
.mux = { CGU_REG_PCMCDR, 30, 2 },
.div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1, BIT(0) },
.gate = { CGU_REG_CLKGR1, 8 },
},
[JZ4760_CLK_I2S] = {
"i2s", CGU_CLK_DIV | CGU_CLK_MUX,
.parents = { JZ4760_CLK_EXT, -1,
JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
.mux = { CGU_REG_I2SCDR, 30, 2 },
.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1, BIT(0) },
},
[JZ4760_CLK_OTG] = {
"usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4760_CLK_EXT, -1,
JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
.mux = { CGU_REG_USBCDR, 30, 2 },
.div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 },
.gate = { CGU_REG_CLKGR0, 2 },
},
/* Those divided clocks can connect to EXT or PLL0 */
[JZ4760_CLK_MMC_MUX] = {
"mmc_mux", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, },
.mux = { CGU_REG_MSCCDR, 31, 1 },
.div = { CGU_REG_MSCCDR, 0, 1, 6, -1, -1, -1, BIT(0) },
},
[JZ4760_CLK_SSI_MUX] = {
"ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
.parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, },
.mux = { CGU_REG_SSICDR, 31, 1 },
.div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1, BIT(0) },
},
/* These divided clock can connect to PLL0 only */
[JZ4760_CLK_CIM] = {
"cim", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4760_CLK_PLL0_HALF },
.div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
.gate = { CGU_REG_CLKGR0, 26 },
},
/* Gate-only clocks */
[JZ4760_CLK_SSI0] = {
"ssi0", CGU_CLK_GATE,
.parents = { JZ4760_CLK_SSI_MUX, },
.gate = { CGU_REG_CLKGR0, 4 },
},
[JZ4760_CLK_SSI1] = {
"ssi1", CGU_CLK_GATE,
.parents = { JZ4760_CLK_SSI_MUX, },
.gate = { CGU_REG_CLKGR0, 19 },
},
[JZ4760_CLK_SSI2] = {
"ssi2", CGU_CLK_GATE,
.parents = { JZ4760_CLK_SSI_MUX, },
.gate = { CGU_REG_CLKGR0, 20 },
},
[JZ4760_CLK_DMA] = {
"dma", CGU_CLK_GATE,
.parents = { JZ4760_CLK_H2CLK, },
.gate = { CGU_REG_CLKGR0, 21 },
},
[JZ4760_CLK_I2C0] = {
"i2c0", CGU_CLK_GATE,
.parents = { JZ4760_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 5 },
},
[JZ4760_CLK_I2C1] = {
"i2c1", CGU_CLK_GATE,
.parents = { JZ4760_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 6 },
},
[JZ4760_CLK_UART0] = {
"uart0", CGU_CLK_GATE,
.parents = { JZ4760_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 15 },
},
[JZ4760_CLK_UART1] = {
"uart1", CGU_CLK_GATE,
.parents = { JZ4760_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 16 },
},
[JZ4760_CLK_UART2] = {
"uart2", CGU_CLK_GATE,
.parents = { JZ4760_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 17 },
},
[JZ4760_CLK_UART3] = {
"uart3", CGU_CLK_GATE,
.parents = { JZ4760_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 18 },
},
[JZ4760_CLK_IPU] = {
"ipu", CGU_CLK_GATE,
.parents = { JZ4760_CLK_HCLK, },
.gate = { CGU_REG_CLKGR0, 29 },
},
[JZ4760_CLK_ADC] = {
"adc", CGU_CLK_GATE,
.parents = { JZ4760_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 14 },
},
[JZ4760_CLK_AIC] = {
"aic", CGU_CLK_GATE,
.parents = { JZ4760_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 8 },
},
[JZ4760_CLK_VPU] = {
"vpu", CGU_CLK_GATE,
.parents = { JZ4760_CLK_HCLK, },
.gate = { CGU_REG_LCR, 30, false, 150 },
},
[JZ4760_CLK_MMC0] = {
"mmc0", CGU_CLK_GATE,
.parents = { JZ4760_CLK_MMC_MUX, },
.gate = { CGU_REG_CLKGR0, 3 },
},
[JZ4760_CLK_MMC1] = {
"mmc1", CGU_CLK_GATE,
.parents = { JZ4760_CLK_MMC_MUX, },
.gate = { CGU_REG_CLKGR0, 11 },
},
[JZ4760_CLK_MMC2] = {
"mmc2", CGU_CLK_GATE,
.parents = { JZ4760_CLK_MMC_MUX, },
.gate = { CGU_REG_CLKGR0, 12 },
},
[JZ4760_CLK_UHC_PHY] = {
"uhc_phy", CGU_CLK_GATE,
.parents = { JZ4760_CLK_UHC, },
.gate = { CGU_REG_OPCR, 5 },
},
[JZ4760_CLK_OTG_PHY] = {
"usb_phy", CGU_CLK_GATE,
.parents = { JZ4760_CLK_OTG },
.gate = { CGU_REG_OPCR, 7, true, 50 },
},
/* Custom clocks */
[JZ4760_CLK_EXT512] = {
"ext/512", CGU_CLK_FIXDIV,
.parents = { JZ4760_CLK_EXT },
.fixdiv = { 512 },
},
[JZ4760_CLK_RTC] = {
"rtc", CGU_CLK_MUX,
.parents = { JZ4760_CLK_EXT512, JZ4760_CLK_OSC32K, },
.mux = { CGU_REG_OPCR, 2, 1},
},
};
static void __init jz4760_cgu_init(struct device_node *np)
{
struct ingenic_cgu *cgu;
int retval;
cgu = ingenic_cgu_new(jz4760_cgu_clocks,
ARRAY_SIZE(jz4760_cgu_clocks), np);
if (!cgu) {
pr_err("%s: failed to initialise CGU\n", __func__);
return;
}
retval = ingenic_cgu_register_clocks(cgu);
if (retval)
pr_err("%s: failed to register CGU Clocks\n", __func__);
ingenic_cgu_register_syscore_ops(cgu);
}
/* We only probe via devicetree, no need for a platform driver */
CLK_OF_DECLARE_DRIVER(jz4760_cgu, "ingenic,jz4760-cgu", jz4760_cgu_init);
/* JZ4760B has some small differences, but we don't implement them. */
CLK_OF_DECLARE_DRIVER(jz4760b_cgu, "ingenic,jz4760b-cgu", jz4760_cgu_init);

15
drivers/clk/ingenic/jz4770-cgu.c
View File

@ -139,8 +139,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
.od_bits = 2,
.od_max = 8,
.od_encoding = pll_od_encoding,
.bypass_reg = CGU_REG_CPPCR1,
.no_bypass_bit = true,
.bypass_bit = -1,
.enable_bit = 7,
.stable_bit = 6,
},
@ -152,7 +151,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
"cclk", CGU_CLK_DIV,
.parents = { JZ4770_CLK_PLL0, },
.div = {
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
jz4770_cgu_cpccr_div_table,
},
},
@ -160,7 +159,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
"h0clk", CGU_CLK_DIV,
.parents = { JZ4770_CLK_PLL0, },
.div = {
CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
jz4770_cgu_cpccr_div_table,
},
},
@ -168,7 +167,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
"h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4770_CLK_PLL0, },
.div = {
CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0,
jz4770_cgu_cpccr_div_table,
},
.gate = { CGU_REG_CLKGR1, 7 },
@ -177,7 +176,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
"h2clk", CGU_CLK_DIV,
.parents = { JZ4770_CLK_PLL0, },
.div = {
CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
jz4770_cgu_cpccr_div_table,
},
},
@ -185,7 +184,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
"c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4770_CLK_PLL0, },
.div = {
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
jz4770_cgu_cpccr_div_table,
},
.gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
@ -194,7 +193,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
"pclk", CGU_CLK_DIV,
.parents = { JZ4770_CLK_PLL0, },
.div = {
CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
jz4770_cgu_cpccr_div_table,
},
},

2
drivers/clk/ingenic/tcu.c
View File

@ -326,6 +326,7 @@ static const struct ingenic_soc_info x1000_soc_info = {
static const struct of_device_id __maybe_unused ingenic_tcu_of_match[] __initconst = {
{ .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
{ .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
{ .compatible = "ingenic,jz4760-tcu", .data = &jz4770_soc_info, },
{ .compatible = "ingenic,jz4770-tcu", .data = &jz4770_soc_info, },
{ .compatible = "ingenic,x1000-tcu", .data = &x1000_soc_info, },
{ /* sentinel */ }
@ -477,5 +478,6 @@ static void __init ingenic_tcu_init(struct device_node *np)
CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init);
CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-tcu", ingenic_tcu_init);
CLK_OF_DECLARE_DRIVER(jz4760_cgu, "ingenic,jz4760-tcu", ingenic_tcu_init);
CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-tcu", ingenic_tcu_init);
CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-tcu", ingenic_tcu_init);

17
drivers/clk/keystone/syscon-clk.c
View File

@ -149,11 +149,28 @@ static const struct ti_syscon_gate_clk_data am654_clk_data[] = {
{ /* Sentinel */ },
};
static const struct ti_syscon_gate_clk_data am64_clk_data[] = {
TI_SYSCON_CLK_GATE("epwm_tbclk0", 0x0, 0),
TI_SYSCON_CLK_GATE("epwm_tbclk1", 0x0, 1),
TI_SYSCON_CLK_GATE("epwm_tbclk2", 0x0, 2),
TI_SYSCON_CLK_GATE("epwm_tbclk3", 0x0, 3),
TI_SYSCON_CLK_GATE("epwm_tbclk4", 0x0, 4),
TI_SYSCON_CLK_GATE("epwm_tbclk5", 0x0, 5),
TI_SYSCON_CLK_GATE("epwm_tbclk6", 0x0, 6),
TI_SYSCON_CLK_GATE("epwm_tbclk7", 0x0, 7),
TI_SYSCON_CLK_GATE("epwm_tbclk8", 0x0, 8),
{ /* Sentinel */ },
};
static const struct of_device_id ti_syscon_gate_clk_ids[] = {
{
.compatible = "ti,am654-ehrpwm-tbclk",
.data = &am654_clk_data,
},
{
.compatible = "ti,am64-epwm-tbclk",
.data = &am64_clk_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, ti_syscon_gate_clk_ids);

5
drivers/clk/meson/axg-audio.c
View File

@ -1665,8 +1665,7 @@ static int devm_clk_get_enable(struct device *dev, char *id)
clk = devm_clk_get(dev, id);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
if (ret != -EPROBE_DEFER)
dev_err(dev, "failed to get %s", id);
dev_err_probe(dev, ret, "failed to get %s", id);
return ret;
}
@ -1811,7 +1810,7 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
ret = device_reset(dev);
if (ret) {
dev_err(dev, "failed to reset device\n");
dev_err_probe(dev, ret, "failed to reset device\n");
return ret;
}

26
drivers/clk/meson/clk-pll.c
View File

@ -242,8 +242,8 @@ static int meson_clk_get_pll_settings(unsigned long rate,
return best ? 0 : -EINVAL;
}
static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
static int meson_clk_pll_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
@ -251,22 +251,26 @@ static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long round;
int ret;
ret = meson_clk_get_pll_settings(rate, *parent_rate, &m, &n, pll);
ret = meson_clk_get_pll_settings(req->rate, req->best_parent_rate,
&m, &n, pll);
if (ret)
return meson_clk_pll_recalc_rate(hw, *parent_rate);
return ret;
round = __pll_params_to_rate(*parent_rate, m, n, 0, pll);
round = __pll_params_to_rate(req->best_parent_rate, m, n, 0, pll);
if (!MESON_PARM_APPLICABLE(&pll->frac) || rate == round)
return round;
if (!MESON_PARM_APPLICABLE(&pll->frac) || req->rate == round) {
req->rate = round;
return 0;
}
/*
* The rate provided by the setting is not an exact match, let's
* try to improve the result using the fractional parameter
*/
frac = __pll_params_with_frac(rate, *parent_rate, m, n, pll);
frac = __pll_params_with_frac(req->rate, req->best_parent_rate, m, n, pll);
req->rate = __pll_params_to_rate(req->best_parent_rate, m, n, frac, pll);
return __pll_params_to_rate(*parent_rate, m, n, frac, pll);
return 0;
}
static int meson_clk_pll_wait_lock(struct clk_hw *hw)
@ -419,7 +423,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
*/
const struct clk_ops meson_clk_pcie_pll_ops = {
.recalc_rate = meson_clk_pll_recalc_rate,
.round_rate = meson_clk_pll_round_rate,
.determine_rate = meson_clk_pll_determine_rate,
.is_enabled = meson_clk_pll_is_enabled,
.enable = meson_clk_pcie_pll_enable,
.disable = meson_clk_pll_disable
@ -429,7 +433,7 @@ EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops);
const struct clk_ops meson_clk_pll_ops = {
.init = meson_clk_pll_init,
.recalc_rate = meson_clk_pll_recalc_rate,
.round_rate = meson_clk_pll_round_rate,
.determine_rate = meson_clk_pll_determine_rate,
.set_rate = meson_clk_pll_set_rate,
.is_enabled = meson_clk_pll_is_enabled,
.enable = meson_clk_pll_enable,

8
drivers/clk/meson/g12a.c
View File

@ -1603,7 +1603,7 @@ static struct clk_regmap g12b_cpub_clk_trace = {
};
static const struct pll_mult_range g12a_gp0_pll_mult_range = {
.min = 55,
.min = 125,
.max = 255,
};
@ -4723,6 +4723,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
[CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
[CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
[CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
[CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
[CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
[CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
[CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
[CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
[CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,

21
drivers/clk/qcom/Kconfig
View File

@ -210,6 +210,13 @@ config MSM_LCC_8960
Say Y if you want to use audio devices such as i2s, pcm,
SLIMBus, etc.
config MDM_GCC_9607
tristate "MDM9607 Global Clock Controller"
help
Support for the global clock controller on mdm9607 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, SD/eMMC, etc.
config MDM_GCC_9615
tristate "MDM9615 Global Clock Controller"
help
@ -483,6 +490,13 @@ config SDX_GCC_55
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_CAMCC_8250
tristate "SM8250 Camera Clock Controller"
select SM_GCC_8250
help
Support for the camera clock controller on SM8250 devices.
Say Y if you want to support camera devices and camera functionality.
config SM_DISPCC_8250
tristate "SM8150 and SM8250 Display Clock Controller"
depends on SM_GCC_8150 || SM_GCC_8250
@ -492,6 +506,13 @@ config SM_DISPCC_8250
Say Y if you want to support display devices and functionality such as
splash screen.
config SM_GCC_6125
tristate "SM6125 Global Clock Controller"
help
Support for the global clock controller on SM6125 devices.
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_GCC_8150
tristate "SM8150 Global Clock Controller"
help

3
drivers/clk/qcom/Makefile
View File

@ -27,6 +27,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
@ -73,7 +74,9 @@ obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o

18
drivers/clk/qcom/apcs-sdx55.c
View File

@ -57,7 +57,7 @@ static int qcom_apcs_sdx55_clk_probe(struct platform_device *pdev)
regmap = dev_get_regmap(parent, NULL);
if (!regmap) {
dev_err_probe(dev, -ENODEV, "Failed to get parent regmap\n");
dev_err(dev, "Failed to get parent regmap\n");
return -ENODEV;
}
@ -80,19 +80,15 @@ static int qcom_apcs_sdx55_clk_probe(struct platform_device *pdev)
a7cc->parent_map = apcs_mux_clk_parent_map;
a7cc->pclk = devm_clk_get(parent, "pll");
if (IS_ERR(a7cc->pclk)) {
ret = PTR_ERR(a7cc->pclk);
if (ret != -EPROBE_DEFER)
dev_err_probe(dev, ret, "Failed to get PLL clk\n");
return ret;
}
if (IS_ERR(a7cc->pclk))
return dev_err_probe(dev, PTR_ERR(a7cc->pclk),
"Failed to get PLL clk\n");
a7cc->clk_nb.notifier_call = a7cc_notifier_cb;
ret = clk_notifier_register(a7cc->pclk, &a7cc->clk_nb);
if (ret) {
dev_err_probe(dev, ret, "Failed to register clock notifier\n");
return ret;
}
if (ret)
return dev_err_probe(dev, ret,
"Failed to register clock notifier\n");
ret = devm_clk_register_regmap(dev, &a7cc->clkr);
if (ret) {

2456
drivers/clk/qcom/camcc-sm8250.c Normal file
View File

File diff suppressed because it is too large Load Diff

176
drivers/clk/qcom/clk-alpha-pll.c
View File

@ -126,6 +126,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL_U] = 0x1c,
[PLL_OFF_STATUS] = 0x2c,
},
[CLK_ALPHA_PLL_TYPE_ZONDA] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x0c,
[PLL_OFF_CONFIG_CTL] = 0x10,
[PLL_OFF_CONFIG_CTL_U] = 0x14,
[PLL_OFF_CONFIG_CTL_U1] = 0x18,
[PLL_OFF_TEST_CTL] = 0x1c,
[PLL_OFF_TEST_CTL_U] = 0x20,
[PLL_OFF_TEST_CTL_U1] = 0x24,
[PLL_OFF_OPMODE] = 0x28,
[PLL_OFF_STATUS] = 0x38,
},
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
@ -162,6 +175,11 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
#define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
/* ZONDA PLL specific */
#define ZONDA_PLL_OUT_MASK 0xf
#define ZONDA_STAY_IN_CFA BIT(16)
#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
#define pll_alpha_width(p) \
((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
@ -208,6 +226,9 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
#define wait_for_pll_enable_lock(pll) \
wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
#define wait_for_zonda_pll_freq_lock(pll) \
wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
#define wait_for_pll_disable(pll) \
wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
@ -1234,7 +1255,7 @@ static int alpha_pll_fabia_prepare(struct clk_hw *hw)
return ret;
/* Setup PLL for calibration frequency */
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), cal_l);
regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
/* Bringup the PLL at calibration frequency */
ret = clk_alpha_pll_enable(hw);
@ -1777,3 +1798,156 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
};
EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);
/* Disable PLL output */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
/* Set operation mode to OFF */
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
/* Place the PLL in STANDBY mode */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
}
EXPORT_SYMBOL_GPL(clk_zonda_pll_configure);
static int clk_zonda_pll_enable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct regmap *regmap = pll->clkr.regmap;
u32 val;
int ret;
regmap_read(regmap, PLL_MODE(pll), &val);
/* If in FSM mode, just vote for it */
if (val & PLL_VOTE_FSM_ENA) {
ret = clk_enable_regmap(hw);
if (ret)
return ret;
return wait_for_pll_enable_active(pll);
}
/* Get the PLL out of bypass mode */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
/*
* H/W requires a 1us delay between disabling the bypass and
* de-asserting the reset.
*/
udelay(1);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
/* Set operation mode to RUN */
regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
regmap_read(regmap, PLL_TEST_CTL(pll), &val);
/* If cfa mode then poll for freq lock */
if (val & ZONDA_STAY_IN_CFA)
ret = wait_for_zonda_pll_freq_lock(pll);
else
ret = wait_for_pll_enable_lock(pll);
if (ret)
return ret;
/* Enable the PLL outputs */
regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
/* Enable the global PLL outputs */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
return 0;
}
static void clk_zonda_pll_disable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct regmap *regmap = pll->clkr.regmap;
u32 val;
regmap_read(regmap, PLL_MODE(pll), &val);
/* If in FSM mode, just unvote it */
if (val & PLL_VOTE_FSM_ENA) {
clk_disable_regmap(hw);
return;
}
/* Disable the global PLL output */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
/* Disable the PLL outputs */
regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
/* Put the PLL in bypass and reset */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
/* Place the PLL mode in OFF state */
regmap_write(regmap, PLL_OPMODE(pll), 0x0);
}
static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
unsigned long rrate;
u32 test_ctl_val;
u32 l, alpha_width = pll_alpha_width(pll);
u64 a;
int ret;
rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
ret = alpha_pll_check_rate_margin(hw, rrate, rate);
if (ret < 0)
return ret;
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
/* Wait before polling for the frequency latch */
udelay(5);
/* Read stay in cfa mode */
regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
/* If cfa mode then poll for freq lock */
if (test_ctl_val & ZONDA_STAY_IN_CFA)
ret = wait_for_zonda_pll_freq_lock(pll);
else
ret = wait_for_pll_enable_lock(pll);
if (ret)
return ret;
/* Wait for PLL output to stabilize */
udelay(100);
return 0;
}
const struct clk_ops clk_alpha_pll_zonda_ops = {
.enable = clk_zonda_pll_enable,
.disable = clk_zonda_pll_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = clk_zonda_pll_set_rate,
};
EXPORT_SYMBOL(clk_alpha_pll_zonda_ops);

6
drivers/clk/qcom/clk-alpha-pll.h
View File

@ -16,6 +16,7 @@ enum {
CLK_ALPHA_PLL_TYPE_TRION,
CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
CLK_ALPHA_PLL_TYPE_AGERA,
CLK_ALPHA_PLL_TYPE_ZONDA,
CLK_ALPHA_PLL_TYPE_MAX,
};
@ -148,6 +149,9 @@ extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
extern const struct clk_ops clk_alpha_pll_zonda_ops;
#define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
@ -159,6 +163,8 @@ void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
#define clk_lucid_pll_configure(pll, regmap, config) \
clk_trion_pll_configure(pll, regmap, config)
void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
#endif

81
drivers/clk/qcom/clk-rcg2.c
View File

@ -357,6 +357,83 @@ static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw,
return __clk_rcg2_set_rate(hw, rate, FLOOR);
}
static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
u32 notn_m, n, m, d, not2d, mask;
if (!rcg->mnd_width) {
/* 50 % duty-cycle for Non-MND RCGs */
duty->num = 1;
duty->den = 2;
return 0;
}
regmap_read(rcg->clkr.regmap, RCG_D_OFFSET(rcg), &not2d);
regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &notn_m);
if (!not2d && !m && !notn_m) {
/* 50 % duty-cycle always */
duty->num = 1;
duty->den = 2;
return 0;
}
mask = BIT(rcg->mnd_width) - 1;
d = ~(not2d) & mask;
d = DIV_ROUND_CLOSEST(d, 2);
n = (~(notn_m) + m) & mask;
duty->num = d;
duty->den = n;
return 0;
}
static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
u32 notn_m, n, m, d, not2d, mask, duty_per;
int ret;
/* Duty-cycle cannot be modified for non-MND RCGs */
if (!rcg->mnd_width)
return -EINVAL;
mask = BIT(rcg->mnd_width) - 1;
regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &notn_m);
regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
n = (~(notn_m) + m) & mask;
duty_per = (duty->num * 100) / duty->den;
/* Calculate 2d value */
d = DIV_ROUND_CLOSEST(n * duty_per * 2, 100);
/* Check bit widths of 2d. If D is too big reduce duty cycle. */
if (d > mask)
d = mask;
if ((d / 2) > (n - m))
d = (n - m) * 2;
else if ((d / 2) < (m / 2))
d = m;
not2d = ~d & mask;
ret = regmap_update_bits(rcg->clkr.regmap, RCG_D_OFFSET(rcg), mask,
not2d);
if (ret)
return ret;
return update_config(rcg);
}
const struct clk_ops clk_rcg2_ops = {
.is_enabled = clk_rcg2_is_enabled,
.get_parent = clk_rcg2_get_parent,
@ -365,6 +442,8 @@ const struct clk_ops clk_rcg2_ops = {
.determine_rate = clk_rcg2_determine_rate,
.set_rate = clk_rcg2_set_rate,
.set_rate_and_parent = clk_rcg2_set_rate_and_parent,
.get_duty_cycle = clk_rcg2_get_duty_cycle,
.set_duty_cycle = clk_rcg2_set_duty_cycle,
};
EXPORT_SYMBOL_GPL(clk_rcg2_ops);
@ -376,6 +455,8 @@ const struct clk_ops clk_rcg2_floor_ops = {
.determine_rate = clk_rcg2_determine_floor_rate,
.set_rate = clk_rcg2_set_floor_rate,
.set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent,
.get_duty_cycle = clk_rcg2_get_duty_cycle,
.set_duty_cycle = clk_rcg2_set_duty_cycle,
};
EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);

673
drivers/clk/qcom/clk-smd-rpm.c
View File

@ -39,7 +39,10 @@
.hw.init = &(struct clk_init_data){ \
.ops = &clk_smd_rpm_ops, \
.name = #_name, \
.parent_names = (const char *[]){ "xo_board" }, \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
.num_parents = 1, \
}, \
}; \
@ -54,7 +57,10 @@
.hw.init = &(struct clk_init_data){ \
.ops = &clk_smd_rpm_ops, \
.name = #_active, \
.parent_names = (const char *[]){ "xo_board" }, \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
.num_parents = 1, \
}, \
}
@ -73,7 +79,10 @@
.hw.init = &(struct clk_init_data){ \
.ops = &clk_smd_rpm_branch_ops, \
.name = #_name, \
.parent_names = (const char *[]){ "xo_board" }, \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
.num_parents = 1, \
}, \
}; \
@ -89,7 +98,10 @@
.hw.init = &(struct clk_init_data){ \
.ops = &clk_smd_rpm_branch_ops, \
.name = #_active, \
.parent_names = (const char *[]){ "xo_board" }, \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
.num_parents = 1, \
}, \
}
@ -406,7 +418,6 @@ static const struct clk_ops clk_smd_rpm_branch_ops = {
.unprepare = clk_smd_rpm_unprepare,
};
/* msm8916 */
DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
@ -452,48 +463,35 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
.num_clks = ARRAY_SIZE(msm8916_clks),
};
/* msm8936 */
DEFINE_CLK_SMD_RPM(msm8936, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8936, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
DEFINE_CLK_SMD_RPM(msm8936, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
DEFINE_CLK_SMD_RPM_QDSS(msm8936, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, bb_clk1, bb_clk1_a, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, bb_clk2, bb_clk2_a, 2);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, rf_clk1, rf_clk1_a, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, rf_clk2, rf_clk2_a, 5);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, bb_clk1_pin, bb_clk1_a_pin, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, bb_clk2_pin, bb_clk2_a_pin, 2);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, rf_clk1_pin, rf_clk1_a_pin, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, rf_clk2_pin, rf_clk2_a_pin, 5);
static struct clk_smd_rpm *msm8936_clks[] = {
[RPM_SMD_PCNOC_CLK] = &msm8936_pcnoc_clk,
[RPM_SMD_PCNOC_A_CLK] = &msm8936_pcnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &msm8936_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8936_snoc_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8936_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8936_bimc_a_clk,
[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
[RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_clk,
[RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
[RPM_SMD_SYSMMNOC_CLK] = &msm8936_sysmmnoc_clk,
[RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk,
[RPM_SMD_QDSS_CLK] = &msm8936_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8936_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &msm8936_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &msm8936_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &msm8936_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &msm8936_bb_clk2_a,
[RPM_SMD_RF_CLK1] = &msm8936_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &msm8936_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &msm8936_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &msm8936_rf_clk2_a,
[RPM_SMD_BB_CLK1_PIN] = &msm8936_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &msm8936_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &msm8936_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &msm8936_bb_clk2_a_pin,
[RPM_SMD_RF_CLK1_PIN] = &msm8936_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &msm8936_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &msm8936_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &msm8936_rf_clk2_a_pin,
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
[RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
@ -501,15 +499,10 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
.num_clks = ARRAY_SIZE(msm8936_clks),
};
/* msm8974 */
DEFINE_CLK_SMD_RPM(msm8974, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8974, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3);
DEFINE_CLK_SMD_RPM(msm8974, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
DEFINE_CLK_SMD_RPM_QDSS(msm8974, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4);
@ -525,22 +518,22 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6);
static struct clk_smd_rpm *msm8974_clks[] = {
[RPM_SMD_PNOC_CLK] = &msm8974_pnoc_clk,
[RPM_SMD_PNOC_A_CLK] = &msm8974_pnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &msm8974_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8974_snoc_a_clk,
[RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
[RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
[RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
[RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8974_bimc_clk,
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
[RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src,
[RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src,
[RPM_SMD_BIMC_A_CLK] = &msm8974_bimc_a_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
[RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
[RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
[RPM_SMD_QDSS_CLK] = &msm8974_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8974_qdss_a_clk,
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
[RPM_SMD_CXO_D0] = &msm8974_cxo_d0,
[RPM_SMD_CXO_D0_A] = &msm8974_cxo_d0_a,
[RPM_SMD_CXO_D1] = &msm8974_cxo_d1,
@ -574,46 +567,33 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
.num_clks = ARRAY_SIZE(msm8974_clks),
};
/* msm8976 */
DEFINE_CLK_SMD_RPM(msm8976, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8976, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
DEFINE_CLK_SMD_RPM(msm8976, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
QCOM_SMD_RPM_BUS_CLK, 2);
DEFINE_CLK_SMD_RPM(msm8976, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
DEFINE_CLK_SMD_RPM_QDSS(msm8976, qdss_clk, qdss_a_clk,
QCOM_SMD_RPM_MISC_CLK, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, bb_clk1, bb_clk1_a, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, bb_clk2, bb_clk2_a, 2);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, rf_clk2, rf_clk2_a, 5);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, div_clk2, div_clk2_a, 12);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8976, bb_clk1_pin, bb_clk1_a_pin, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8976, bb_clk2_pin, bb_clk2_a_pin, 2);
static struct clk_smd_rpm *msm8976_clks[] = {
[RPM_SMD_PCNOC_CLK] = &msm8976_pcnoc_clk,
[RPM_SMD_PCNOC_A_CLK] = &msm8976_pcnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &msm8976_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8976_snoc_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8976_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8976_bimc_a_clk,
[RPM_SMD_QDSS_CLK] = &msm8976_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8976_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &msm8976_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &msm8976_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &msm8976_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &msm8976_bb_clk2_a,
[RPM_SMD_RF_CLK2] = &msm8976_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &msm8976_rf_clk2_a,
[RPM_SMD_BB_CLK1_PIN] = &msm8976_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &msm8976_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &msm8976_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &msm8976_bb_clk2_a_pin,
[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
[RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
[RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
[RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8976_mmssnoc_ahb_clk,
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8976_mmssnoc_ahb_a_clk,
[RPM_SMD_DIV_CLK2] = &msm8976_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &msm8976_div_clk2_a,
[RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
[RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
};
@ -623,78 +603,55 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
.num_clks = ARRAY_SIZE(msm8976_clks),
};
/* msm8992 */
DEFINE_CLK_SMD_RPM(msm8992, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8992, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
DEFINE_CLK_SMD_RPM(msm8992, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8992, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
DEFINE_CLK_SMD_RPM(msm8992, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
DEFINE_CLK_SMD_RPM(msm8992, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, bb_clk1, bb_clk1_a, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, bb_clk1_pin, bb_clk1_a_pin, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, bb_clk2, bb_clk2_a, 2);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, bb_clk2_pin, bb_clk2_a_pin, 2);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk1, div_clk1_a, 11);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk2, div_clk2_a, 12);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13);
DEFINE_CLK_SMD_RPM(msm8992, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8);
DEFINE_CLK_SMD_RPM(msm8992, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
QCOM_SMD_RPM_BUS_CLK, 3);
DEFINE_CLK_SMD_RPM_QDSS(msm8992, qdss_clk, qdss_a_clk,
QCOM_SMD_RPM_MISC_CLK, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk1, rf_clk1_a, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk2, rf_clk2_a, 5);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, rf_clk1_pin, rf_clk1_a_pin, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, rf_clk2_pin, rf_clk2_a_pin, 5);
DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
static struct clk_smd_rpm *msm8992_clks[] = {
[RPM_SMD_PNOC_CLK] = &msm8992_pnoc_clk,
[RPM_SMD_PNOC_A_CLK] = &msm8992_pnoc_a_clk,
[RPM_SMD_OCMEMGX_CLK] = &msm8992_ocmemgx_clk,
[RPM_SMD_OCMEMGX_A_CLK] = &msm8992_ocmemgx_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8992_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8992_bimc_a_clk,
[RPM_SMD_CNOC_CLK] = &msm8992_cnoc_clk,
[RPM_SMD_CNOC_A_CLK] = &msm8992_cnoc_a_clk,
[RPM_SMD_GFX3D_CLK_SRC] = &msm8992_gfx3d_clk_src,
[RPM_SMD_GFX3D_A_CLK_SRC] = &msm8992_gfx3d_a_clk_src,
[RPM_SMD_SNOC_CLK] = &msm8992_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8992_snoc_a_clk,
[RPM_SMD_BB_CLK1] = &msm8992_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &msm8992_bb_clk1_a,
[RPM_SMD_BB_CLK1_PIN] = &msm8992_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &msm8992_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2] = &msm8992_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &msm8992_bb_clk2_a,
[RPM_SMD_BB_CLK2_PIN] = &msm8992_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &msm8992_bb_clk2_a_pin,
[RPM_SMD_DIV_CLK1] = &msm8992_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &msm8992_div_clk1_a,
[RPM_SMD_DIV_CLK2] = &msm8992_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &msm8992_div_clk2_a,
[RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
[RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
[RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
[RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
[RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
[RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
[RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src,
[RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src,
[RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
[RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
[RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
[RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
[RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
[RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
[RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
[RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
[RPM_SMD_IPA_CLK] = &msm8992_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &msm8992_ipa_a_clk,
[RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
[RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
[RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8992_mmssnoc_ahb_clk,
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8992_mmssnoc_ahb_a_clk,
[RPM_SMD_QDSS_CLK] = &msm8992_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8992_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &msm8992_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &msm8992_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &msm8992_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &msm8992_rf_clk2_a,
[RPM_SMD_RF_CLK1_PIN] = &msm8992_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &msm8992_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &msm8992_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &msm8992_rf_clk2_a_pin,
[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
[RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
[RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
@ -706,83 +663,55 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
.num_clks = ARRAY_SIZE(msm8992_clks),
};
/* msm8994 */
DEFINE_CLK_SMD_RPM(msm8994, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8994, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
DEFINE_CLK_SMD_RPM(msm8994, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8994, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
DEFINE_CLK_SMD_RPM(msm8994, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
DEFINE_CLK_SMD_RPM(msm8994, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, bb_clk1, bb_clk1_a, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, bb_clk1_pin, bb_clk1_a_pin, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, bb_clk2, bb_clk2_a, 2);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, bb_clk2_pin, bb_clk2_a_pin, 2);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk1, div_clk1_a, 11);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk2, div_clk2_a, 12);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk3, div_clk3_a, 13);
DEFINE_CLK_SMD_RPM(msm8994, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, ln_bb_clk, ln_bb_a_clk, 8);
DEFINE_CLK_SMD_RPM(msm8994, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
QCOM_SMD_RPM_BUS_CLK, 3);
DEFINE_CLK_SMD_RPM_QDSS(msm8994, qdss_clk, qdss_a_clk,
QCOM_SMD_RPM_MISC_CLK, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk1, rf_clk1_a, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk2, rf_clk2_a, 5);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, rf_clk1_pin, rf_clk1_a_pin, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, rf_clk2_pin, rf_clk2_a_pin, 5);
DEFINE_CLK_SMD_RPM(msm8994, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8994, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);
static struct clk_smd_rpm *msm8994_clks[] = {
[RPM_SMD_PNOC_CLK] = &msm8994_pnoc_clk,
[RPM_SMD_PNOC_A_CLK] = &msm8994_pnoc_a_clk,
[RPM_SMD_OCMEMGX_CLK] = &msm8994_ocmemgx_clk,
[RPM_SMD_OCMEMGX_A_CLK] = &msm8994_ocmemgx_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8994_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8994_bimc_a_clk,
[RPM_SMD_CNOC_CLK] = &msm8994_cnoc_clk,
[RPM_SMD_CNOC_A_CLK] = &msm8994_cnoc_a_clk,
[RPM_SMD_GFX3D_CLK_SRC] = &msm8994_gfx3d_clk_src,
[RPM_SMD_GFX3D_A_CLK_SRC] = &msm8994_gfx3d_a_clk_src,
[RPM_SMD_SNOC_CLK] = &msm8994_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8994_snoc_a_clk,
[RPM_SMD_BB_CLK1] = &msm8994_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &msm8994_bb_clk1_a,
[RPM_SMD_BB_CLK1_PIN] = &msm8994_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &msm8994_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2] = &msm8994_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &msm8994_bb_clk2_a,
[RPM_SMD_BB_CLK2_PIN] = &msm8994_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &msm8994_bb_clk2_a_pin,
[RPM_SMD_DIV_CLK1] = &msm8994_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &msm8994_div_clk1_a,
[RPM_SMD_DIV_CLK2] = &msm8994_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &msm8994_div_clk2_a,
[RPM_SMD_DIV_CLK3] = &msm8994_div_clk3,
[RPM_SMD_DIV_A_CLK3] = &msm8994_div_clk3_a,
[RPM_SMD_IPA_CLK] = &msm8994_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &msm8994_ipa_a_clk,
[RPM_SMD_LN_BB_CLK] = &msm8994_ln_bb_clk,
[RPM_SMD_LN_BB_A_CLK] = &msm8994_ln_bb_a_clk,
[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8994_mmssnoc_ahb_clk,
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8994_mmssnoc_ahb_a_clk,
[RPM_SMD_QDSS_CLK] = &msm8994_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8994_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &msm8994_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &msm8994_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &msm8994_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &msm8994_rf_clk2_a,
[RPM_SMD_RF_CLK1_PIN] = &msm8994_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &msm8994_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &msm8994_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &msm8994_rf_clk2_a_pin,
[RPM_SMD_CE1_CLK] = &msm8994_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &msm8994_ce1_a_clk,
[RPM_SMD_CE2_CLK] = &msm8994_ce2_clk,
[RPM_SMD_CE2_A_CLK] = &msm8994_ce2_a_clk,
[RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
[RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
[RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
[RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
[RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
[RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
[RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src,
[RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src,
[RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
[RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
[RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
[RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
[RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
[RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
[RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
[RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
[RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
[RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
[RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
[RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
[RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
[RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
[RPM_SMD_CE3_CLK] = &msm8994_ce3_clk,
[RPM_SMD_CE3_A_CLK] = &msm8994_ce3_a_clk,
};
@ -792,79 +721,58 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
.num_clks = ARRAY_SIZE(msm8994_clks),
};
/* msm8996 */
DEFINE_CLK_SMD_RPM(msm8996, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8996, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
DEFINE_CLK_SMD_RPM(msm8996, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
DEFINE_CLK_SMD_RPM(msm8996, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
QCOM_SMD_RPM_MMAXI_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8996, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8996, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk,
QCOM_SMD_RPM_AGGR_CLK, 1, 1000);
DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk,
QCOM_SMD_RPM_AGGR_CLK, 2, 1000);
DEFINE_CLK_SMD_RPM_QDSS(msm8996, qdss_clk, qdss_a_clk,
QCOM_SMD_RPM_MISC_CLK, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk1, bb_clk1_a, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk2, bb_clk2_a, 2);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk1, rf_clk1_a, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk2, rf_clk2_a, 5);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, ln_bb_clk, ln_bb_a_clk, 8);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk1, div_clk1_a, 0xb);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk2, div_clk2_a, 0xc);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk3, div_clk3_a, 0xd);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk1_pin, bb_clk1_a_pin, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin, 2);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin, 5);
static struct clk_smd_rpm *msm8996_clks[] = {
[RPM_SMD_PCNOC_CLK] = &msm8996_pcnoc_clk,
[RPM_SMD_PCNOC_A_CLK] = &msm8996_pcnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &msm8996_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8996_snoc_a_clk,
[RPM_SMD_CNOC_CLK] = &msm8996_cnoc_clk,
[RPM_SMD_CNOC_A_CLK] = &msm8996_cnoc_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8996_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8996_bimc_a_clk,
[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
[RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
[RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
[RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
[RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
[RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
[RPM_SMD_IPA_CLK] = &msm8996_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &msm8996_ipa_a_clk,
[RPM_SMD_CE1_CLK] = &msm8996_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &msm8996_ce1_a_clk,
[RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
[RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
[RPM_SMD_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk,
[RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk,
[RPM_SMD_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk,
[RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk,
[RPM_SMD_QDSS_CLK] = &msm8996_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8996_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &msm8996_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &msm8996_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &msm8996_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &msm8996_bb_clk2_a,
[RPM_SMD_RF_CLK1] = &msm8996_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &msm8996_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &msm8996_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &msm8996_rf_clk2_a,
[RPM_SMD_LN_BB_CLK] = &msm8996_ln_bb_clk,
[RPM_SMD_LN_BB_A_CLK] = &msm8996_ln_bb_a_clk,
[RPM_SMD_DIV_CLK1] = &msm8996_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &msm8996_div_clk1_a,
[RPM_SMD_DIV_CLK2] = &msm8996_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &msm8996_div_clk2_a,
[RPM_SMD_DIV_CLK3] = &msm8996_div_clk3,
[RPM_SMD_DIV_A_CLK3] = &msm8996_div_clk3_a,
[RPM_SMD_BB_CLK1_PIN] = &msm8996_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &msm8996_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &msm8996_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &msm8996_bb_clk2_a_pin,
[RPM_SMD_RF_CLK1_PIN] = &msm8996_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &msm8996_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &msm8996_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &msm8996_rf_clk2_a_pin,
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
[RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
[RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
[RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
[RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
[RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
[RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
[RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
@ -872,43 +780,29 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
.num_clks = ARRAY_SIZE(msm8996_clks),
};
/* QCS404 */
DEFINE_CLK_SMD_RPM_QDSS(qcs404, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
DEFINE_CLK_SMD_RPM(qcs404, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
DEFINE_CLK_SMD_RPM(qcs404, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
DEFINE_CLK_SMD_RPM(qcs404, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
DEFINE_CLK_SMD_RPM(qcs404, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, rf_clk1, rf_clk1_a, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, rf_clk1_pin, rf_clk1_a_pin, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, ln_bb_clk, ln_bb_a_clk, 8);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8);
static struct clk_smd_rpm *qcs404_clks[] = {
[RPM_SMD_QDSS_CLK] = &qcs404_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &qcs404_qdss_a_clk,
[RPM_SMD_PNOC_CLK] = &qcs404_pnoc_clk,
[RPM_SMD_PNOC_A_CLK] = &qcs404_pnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &qcs404_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &qcs404_snoc_a_clk,
[RPM_SMD_BIMC_CLK] = &qcs404_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &qcs404_bimc_a_clk,
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
[RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
[RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
[RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk,
[RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk,
[RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk,
[RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk,
[RPM_SMD_CE1_CLK] = &qcs404_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &qcs404_ce1_a_clk,
[RPM_SMD_RF_CLK1] = &qcs404_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &qcs404_rf_clk1_a,
[RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk,
[RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_a_clk,
[RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
[RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
[RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
};
static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
@ -916,63 +810,47 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
.num_clks = ARRAY_SIZE(qcs404_clks),
};
/* msm8998 */
DEFINE_CLK_SMD_RPM(msm8998, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8998, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8998, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
DEFINE_CLK_SMD_RPM(msm8998, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
DEFINE_CLK_SMD_RPM(msm8998, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, div_clk1, div_clk1_a, 0xb);
DEFINE_CLK_SMD_RPM(msm8998, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin,
3);
DEFINE_CLK_SMD_RPM(msm8998, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
QCOM_SMD_RPM_MMAXI_CLK, 0);
DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
QCOM_SMD_RPM_AGGR_CLK, 1);
DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
QCOM_SMD_RPM_AGGR_CLK, 2);
DEFINE_CLK_SMD_RPM_QDSS(msm8998, qdss_clk, qdss_a_clk,
QCOM_SMD_RPM_MISC_CLK, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk1, rf_clk1_a, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk2_pin, rf_clk2_a_pin, 5);
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6);
static struct clk_smd_rpm *msm8998_clks[] = {
[RPM_SMD_BIMC_CLK] = &msm8998_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8998_bimc_a_clk,
[RPM_SMD_PCNOC_CLK] = &msm8998_pcnoc_clk,
[RPM_SMD_PCNOC_A_CLK] = &msm8998_pcnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &msm8998_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8998_snoc_a_clk,
[RPM_SMD_CNOC_CLK] = &msm8998_cnoc_clk,
[RPM_SMD_CNOC_A_CLK] = &msm8998_cnoc_a_clk,
[RPM_SMD_CE1_CLK] = &msm8998_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &msm8998_ce1_a_clk,
[RPM_SMD_DIV_CLK1] = &msm8998_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &msm8998_div_clk1_a,
[RPM_SMD_IPA_CLK] = &msm8998_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &msm8998_ipa_a_clk,
[RPM_SMD_LN_BB_CLK1] = &msm8998_ln_bb_clk1,
[RPM_SMD_LN_BB_CLK1_A] = &msm8998_ln_bb_clk1_a,
[RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2,
[RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a,
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
[RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
[RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
[RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
[RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
[RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
[RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
[RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1,
[RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
[RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
[RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
[RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
[RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
[RPM_SMD_MMAXI_CLK] = &msm8998_mmssnoc_axi_rpm_clk,
[RPM_SMD_MMAXI_A_CLK] = &msm8998_mmssnoc_axi_rpm_a_clk,
[RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
[RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
[RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk,
[RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk,
[RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
[RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
[RPM_SMD_QDSS_CLK] = &msm8998_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8998_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &msm8998_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &msm8998_rf_clk1_a,
[RPM_SMD_RF_CLK2_PIN] = &msm8998_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &msm8998_rf_clk2_a_pin,
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
[RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
[RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
[RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
@ -984,72 +862,48 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
.num_clks = ARRAY_SIZE(msm8998_clks),
};
/* sdm660 */
DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
19200000);
DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk,
QCOM_SMD_RPM_BUS_CLK, 0);
DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk,
QCOM_SMD_RPM_MMAXI_CLK, 0);
DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk,
QCOM_SMD_RPM_AGGR_CLK, 2);
DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk,
QCOM_SMD_RPM_MISC_CLK, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_a, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_a, 11);
DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_a, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_a, 2);
DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_a_pin, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin,
ln_bb_clk1_pin_a, 1);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin,
ln_bb_clk2_pin_a, 2);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin,
ln_bb_clk3_pin_a, 3);
static struct clk_smd_rpm *sdm660_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
[RPM_SMD_SNOC_CLK] = &sdm660_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &sdm660_snoc_a_clk,
[RPM_SMD_CNOC_CLK] = &sdm660_cnoc_clk,
[RPM_SMD_CNOC_A_CLK] = &sdm660_cnoc_a_clk,
[RPM_SMD_CNOC_PERIPH_CLK] = &sdm660_cnoc_periph_clk,
[RPM_SMD_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk,
[RPM_SMD_BIMC_CLK] = &sdm660_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &sdm660_bimc_a_clk,
[RPM_SMD_MMSSNOC_AXI_CLK] = &sdm660_mmssnoc_axi_clk,
[RPM_SMD_MMSSNOC_AXI_CLK_A] = &sdm660_mmssnoc_axi_a_clk,
[RPM_SMD_IPA_CLK] = &sdm660_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &sdm660_ipa_a_clk,
[RPM_SMD_CE1_CLK] = &sdm660_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &sdm660_ce1_a_clk,
[RPM_SMD_AGGR2_NOC_CLK] = &sdm660_aggre2_noc_clk,
[RPM_SMD_AGGR2_NOC_A_CLK] = &sdm660_aggre2_noc_a_clk,
[RPM_SMD_QDSS_CLK] = &sdm660_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &sdm660_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &sdm660_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &sdm660_rf_clk1_a,
[RPM_SMD_DIV_CLK1] = &sdm660_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &sdm660_div_clk1_a,
[RPM_SMD_LN_BB_CLK] = &sdm660_ln_bb_clk1,
[RPM_SMD_LN_BB_A_CLK] = &sdm660_ln_bb_clk1_a,
[RPM_SMD_LN_BB_CLK2] = &sdm660_ln_bb_clk2,
[RPM_SMD_LN_BB_CLK2_A] = &sdm660_ln_bb_clk2_a,
[RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
[RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
[RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
[RPM_SMD_CNOC_PERIPH_CLK] = &msm8916_pcnoc_clk,
[RPM_SMD_CNOC_PERIPH_A_CLK] = &msm8916_pcnoc_a_clk,
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
[RPM_SMD_MMSSNOC_AXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
[RPM_SMD_MMSSNOC_AXI_CLK_A] = &msm8996_mmssnoc_axi_rpm_a_clk,
[RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
[RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
[RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
[RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
[RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
[RPM_SMD_LN_BB_CLK] = &msm8916_bb_clk1,
[RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a,
[RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
[RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
[RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
[RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
[RPM_SMD_RF_CLK1_PIN] = &sdm660_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &sdm660_rf_clk1_a_pin,
[RPM_SMD_LN_BB_CLK1_PIN] = &sdm660_ln_bb_clk1_pin,
[RPM_SMD_LN_BB_CLK1_A_PIN] = &sdm660_ln_bb_clk1_pin_a,
[RPM_SMD_LN_BB_CLK2_PIN] = &sdm660_ln_bb_clk2_pin,
[RPM_SMD_LN_BB_CLK2_A_PIN] = &sdm660_ln_bb_clk2_pin_a,
[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
[RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
[RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
[RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
[RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
[RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin,
[RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a,
};
@ -1060,6 +914,7 @@ static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
};
static const struct of_device_id rpm_smd_clk_match_table[] = {
{ .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 },
{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
{ .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },

190
drivers/clk/qcom/dispcc-sm8250.c
View File

@ -26,6 +26,8 @@ enum {
P_DISP_CC_PLL1_OUT_MAIN,
P_DP_PHY_PLL_LINK_CLK,
P_DP_PHY_PLL_VCO_DIV_CLK,
P_EDP_PHY_PLL_LINK_CLK,
P_EDP_PHY_PLL_VCO_DIV_CLK,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_DSI1_PHY_PLL_OUT_BYTECLK,
@ -134,6 +136,18 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .hw = &disp_cc_pll1.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_EDP_PHY_PLL_LINK_CLK, 1 },
{ P_EDP_PHY_PLL_VCO_DIV_CLK, 2},
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "edp_phy_pll_link_clk" },
{ .fw_name = "edp_phy_pll_vco_div_clk" },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
@ -158,6 +172,18 @@ static const struct clk_parent_data disp_cc_parent_data_6[] = {
{ .fw_name = "dsi1_phy_pll_out_dsiclk" },
};
static const struct parent_map disp_cc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
/* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */
};
static const struct clk_parent_data disp_cc_parent_data_7[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &disp_cc_pll1.clkr.hw },
/* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
@ -261,7 +287,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
.name = "disp_cc_mdss_dp_link1_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};
@ -275,7 +301,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.name = "disp_cc_mdss_dp_link_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
.ops = &clk_byte2_ops,
},
};
@ -318,6 +344,153 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
},
};
static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
.cmd_rcgr = 0x228c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_aux_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = {
.cmd_rcgr = 0x22a4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_7,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_gtc_clk_src",
.parent_data = disp_cc_parent_data_7,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
.cmd_rcgr = 0x2270,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_link_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
.cmd_rcgr = 0x2258,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_pixel_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.ops = &clk_dp_ops,
},
};
static struct clk_branch disp_cc_mdss_edp_aux_clk = {
.halt_reg = 0x2078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_edp_gtc_clk = {
.halt_reg = 0x207c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x207c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_gtc_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_gtc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_edp_link_clk = {
.halt_reg = 0x2070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2070,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
.halt_reg = 0x2074,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
.halt_reg = 0x206c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x206c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_pixel_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x2148,
.mnd_width = 0,
@ -987,6 +1160,15 @@ static struct clk_regmap *disp_cc_sm8250_clocks[] = {
[DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr,
[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
[DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr,
[DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr,
[DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr,
[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr,
[DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
[DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
[DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
[DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
[DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
@ -1037,6 +1219,7 @@ static const struct qcom_cc_desc disp_cc_sm8250_desc = {
};
static const struct of_device_id disp_cc_sm8250_match_table[] = {
{ .compatible = "qcom,sc8180x-dispcc" },
{ .compatible = "qcom,sm8150-dispcc" },
{ .compatible = "qcom,sm8250-dispcc" },
{ }
@ -1053,7 +1236,8 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
/* note: trion == lucid, except for the prepare() op */
BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") ||
of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;

1632
drivers/clk/qcom/gcc-mdm9607.c Normal file
View File

File diff suppressed because it is too large Load Diff

169
drivers/clk/qcom/gcc-msm8974.c
View File

@ -719,6 +719,12 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
},
};
static const struct freq_tbl ftbl_gcc_ce1_clk_msm8226[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
{ }
};
static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
@ -761,6 +767,11 @@ static struct clk_rcg2 ce2_clk_src = {
},
};
static const struct freq_tbl ftbl_gcc_gp_clk_msm8226[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static const struct freq_tbl ftbl_gcc_gp_clk[] = {
F(4800000, P_XO, 4, 0, 0),
F(6000000, P_GPLL0, 10, 1, 10),
@ -1955,6 +1966,10 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
.parent_names = (const char *[]){
"system_noc_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@ -1993,6 +2008,20 @@ static struct clk_branch gcc_pdm_ahb_clk = {
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x0cc8,
.clkr = {
.enable_reg = 0x0cc8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x0d04,
.halt_check = BRANCH_HALT_VOTED,
@ -2430,6 +2459,121 @@ static struct gdsc usb_hs_hsic_gdsc = {
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *gcc_msm8226_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_VOTE] = &gpll0_vote,
[GPLL1] = &gpll1.clkr,
[GPLL1_VOTE] = &gpll1_vote,
[CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
[PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
[SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
[CE1_CLK_SRC] = &ce1_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
[USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
[USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
[GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
[GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
[GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
[GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
[GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
};
static const struct qcom_reset_map gcc_msm8226_resets[] = {
[GCC_USB_HS_HSIC_BCR] = { 0x0400 },
[GCC_USB_HS_BCR] = { 0x0480 },
[GCC_USB2A_PHY_BCR] = { 0x04a8 },
};
static struct gdsc *gcc_msm8226_gdscs[] = {
[USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
};
static const struct regmap_config gcc_msm8226_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1a80,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_msm8226_desc = {
.config = &gcc_msm8226_regmap_config,
.clks = gcc_msm8226_clocks,
.num_clks = ARRAY_SIZE(gcc_msm8226_clocks),
.resets = gcc_msm8226_resets,
.num_resets = ARRAY_SIZE(gcc_msm8226_resets),
.gdscs = gcc_msm8226_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8226_gdscs),
};
static struct clk_regmap *gcc_msm8974_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_VOTE] = &gpll0_vote,
@ -2682,13 +2826,22 @@ static const struct qcom_cc_desc gcc_msm8974_desc = {
};
static const struct of_device_id gcc_msm8974_match_table[] = {
{ .compatible = "qcom,gcc-msm8974" },
{ .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL },
{ .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL },
{ .compatible = "qcom,gcc-msm8226", .data = &gcc_msm8226_desc },
{ .compatible = "qcom,gcc-msm8974", .data = &gcc_msm8974_desc },
{ .compatible = "qcom,gcc-msm8974pro", .data = &gcc_msm8974_desc },
{ .compatible = "qcom,gcc-msm8974pro-ac", .data = &gcc_msm8974_desc },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
static void msm8226_clock_override(void)
{
ce1_clk_src.freq_tbl = ftbl_gcc_ce1_clk_msm8226;
gp1_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
gp2_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
gp3_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
}
static void msm8974_pro_clock_override(void)
{
sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4;
@ -2708,16 +2861,18 @@ static int gcc_msm8974_probe(struct platform_device *pdev)
{
int ret;
struct device *dev = &pdev->dev;
bool pro;
const struct of_device_id *id;
id = of_match_device(gcc_msm8974_match_table, dev);
if (!id)
return -ENODEV;
pro = !!(id->data);
if (pro)
msm8974_pro_clock_override();
if (!of_device_is_compatible(dev->of_node, "qcom,gcc-msm8974")) {
if (id->data == &gcc_msm8226_desc)
msm8226_clock_override();
else
msm8974_pro_clock_override();
}
ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
if (ret)

1
drivers/clk/qcom/gcc-sc7280.c
View File

@ -716,6 +716,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(52174000, P_GCC_GPLL0_OUT_MAIN, 1, 2, 23),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),

4190
drivers/clk/qcom/gcc-sm6125.c Normal file
View File

File diff suppressed because it is too large Load Diff

9
drivers/clk/renesas/Kconfig
View File

@ -32,6 +32,7 @@ config CLK_RENESAS
select CLK_R8A77995 if ARCH_R8A77995
select CLK_R8A779A0 if ARCH_R8A779A0
select CLK_R9A06G032 if ARCH_R9A06G032
select CLK_R9A07G044 if ARCH_R9A07G044
select CLK_SH73A0 if ARCH_SH73A0
if CLK_RENESAS
@ -156,6 +157,10 @@ config CLK_R9A06G032
help
This is a driver for R9A06G032 clocks
config CLK_R9A07G044
bool "RZ/G2L clock support" if COMPILE_TEST
select CLK_RZG2L
config CLK_SH73A0
bool "SH-Mobile AG5 clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP
@ -182,6 +187,10 @@ config CLK_RCAR_USB2_CLOCK_SEL
help
This is a driver for R-Car USB2 clock selector
config CLK_RZG2L
bool "Renesas RZ/G2L family clock support" if COMPILE_TEST
select RESET_CONTROLLER
# Generic
config CLK_RENESAS_CPG_MSSR
bool "CPG/MSSR clock support" if COMPILE_TEST

2
drivers/clk/renesas/Makefile
View File

@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
# Family
@ -36,6 +37,7 @@ obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
obj-$(CONFIG_CLK_RZG2L) += renesas-rzg2l-cpg.o
# Generic
obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o

80
drivers/clk/renesas/clk-div6.c
View File

@ -28,8 +28,7 @@
* @hw: handle between common and hardware-specific interfaces
* @reg: IO-remapped register
* @div: divisor value (1-64)
* @src_shift: Shift to access the register bits to select the parent clock
* @src_width: Number of register bits to select the parent clock (may be 0)
* @src_mask: Bitmask covering the register bits to select the parent clock
* @nb: Notifier block to save/restore clock state for system resume
* @parents: Array to map from valid parent clocks indices to hardware indices
*/
@ -37,8 +36,7 @@ struct div6_clock {
struct clk_hw hw;
void __iomem *reg;
unsigned int div;
u32 src_shift;
u32 src_width;
u32 src_mask;
struct notifier_block nb;
u8 parents[];
};
@ -99,15 +97,52 @@ static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
rate = 1;
div = DIV_ROUND_CLOSEST(parent_rate, rate);
return clamp_t(unsigned int, div, 1, 64);
return clamp(div, 1U, 64U);
}
static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
static int cpg_div6_clock_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);
unsigned long prate, calc_rate, diff, best_rate, best_prate;
unsigned int num_parents = clk_hw_get_num_parents(hw);
struct clk_hw *parent, *best_parent = NULL;
unsigned int i, min_div, max_div, div;
unsigned long min_diff = ULONG_MAX;
return *parent_rate / div;
for (i = 0; i < num_parents; i++) {
parent = clk_hw_get_parent_by_index(hw, i);
if (!parent)
continue;
prate = clk_hw_get_rate(parent);
if (!prate)
continue;
min_div = max(DIV_ROUND_UP(prate, req->max_rate), 1UL);
max_div = req->min_rate ? min(prate / req->min_rate, 64UL) : 64;
if (max_div < min_div)
continue;
div = cpg_div6_clock_calc_div(req->rate, prate);
div = clamp(div, min_div, max_div);
calc_rate = prate / div;
diff = calc_rate > req->rate ? calc_rate - req->rate
: req->rate - calc_rate;
if (diff < min_diff) {
best_rate = calc_rate;
best_parent = parent;
best_prate = prate;
min_diff = diff;
}
}
if (!best_parent)
return -EINVAL;
req->best_parent_rate = best_prate;
req->best_parent_hw = best_parent;
req->rate = best_rate;
return 0;
}
static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
@ -133,11 +168,11 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
unsigned int i;
u8 hw_index;
if (clock->src_width == 0)
if (clock->src_mask == 0)
return 0;
hw_index = (readl(clock->reg) >> clock->src_shift) &
(BIT(clock->src_width) - 1);
hw_index = (readl(clock->reg) & clock->src_mask) >>
__ffs(clock->src_mask);
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
if (clock->parents[i] == hw_index)
return i;
@ -151,18 +186,13 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
{
struct div6_clock *clock = to_div6_clock(hw);
u8 hw_index;
u32 mask;
u32 src;
if (index >= clk_hw_get_num_parents(hw))
return -EINVAL;
mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
hw_index = clock->parents[index];
writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift),
clock->reg);
src = clock->parents[index] << __ffs(clock->src_mask);
writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg);
return 0;
}
@ -173,7 +203,7 @@ static const struct clk_ops cpg_div6_clock_ops = {
.get_parent = cpg_div6_clock_get_parent,
.set_parent = cpg_div6_clock_set_parent,
.recalc_rate = cpg_div6_clock_recalc_rate,
.round_rate = cpg_div6_clock_round_rate,
.determine_rate = cpg_div6_clock_determine_rate,
.set_rate = cpg_div6_clock_set_rate,
};
@ -236,17 +266,15 @@ struct clk * __init cpg_div6_register(const char *name,
switch (num_parents) {
case 1:
/* fixed parent clock */
clock->src_shift = clock->src_width = 0;
clock->src_mask = 0;
break;
case 4:
/* clock with EXSRC bits 6-7 */
clock->src_shift = 6;
clock->src_width = 2;
clock->src_mask = GENMASK(7, 6);
break;
case 8:
/* VCLK with EXSRC bits 12-14 */
clock->src_shift = 12;
clock->src_width = 3;
clock->src_mask = GENMASK(14, 12);
break;
default:
pr_err("%s: invalid number of parents for DIV6 clock %s\n",

1
drivers/clk/renesas/r8a77995-cpg-mssr.c
View File

@ -75,6 +75,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
/* Core Clock Outputs */
DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1),
DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),

4
drivers/clk/renesas/r8a779a0-cpg-mssr.c
View File

@ -180,6 +180,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4),
DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4),
DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4),
DEF_MOD("ispcs0", 612, R8A779A0_CLK_S1D1),
DEF_MOD("ispcs1", 613, R8A779A0_CLK_S1D1),
DEF_MOD("ispcs2", 614, R8A779A0_CLK_S1D1),
DEF_MOD("ispcs3", 615, R8A779A0_CLK_S1D1),
DEF_MOD("msi0", 618, R8A779A0_CLK_MSO),
DEF_MOD("msi1", 619, R8A779A0_CLK_MSO),
DEF_MOD("msi2", 620, R8A779A0_CLK_MSO),

25
drivers/clk/renesas/r9a06g032-clocks.c
View File

@ -604,20 +604,19 @@ r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk,
return div;
}
static long
r9a06g032_div_round_rate(struct clk_hw *hw,
unsigned long rate, unsigned long *prate)
static int
r9a06g032_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
u32 div = DIV_ROUND_UP(*prate, rate);
u32 div = DIV_ROUND_UP(req->best_parent_rate, req->rate);
pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__,
hw->clk, rate, *prate, div);
hw->clk, req->rate, req->best_parent_rate, div);
pr_devel(" min %d (%ld) max %d (%ld)\n",
clk->min, DIV_ROUND_UP(*prate, clk->min),
clk->max, DIV_ROUND_UP(*prate, clk->max));
clk->min, DIV_ROUND_UP(req->best_parent_rate, clk->min),
clk->max, DIV_ROUND_UP(req->best_parent_rate, clk->max));
div = r9a06g032_div_clamp_div(clk, rate, *prate);
div = r9a06g032_div_clamp_div(clk, req->rate, req->best_parent_rate);
/*
* this is a hack. Currently the serial driver asks for a clock rate
* that is 16 times the baud rate -- and that is wildly outside the
@ -630,11 +629,13 @@ r9a06g032_div_round_rate(struct clk_hw *hw,
if (clk->index == R9A06G032_DIV_UART ||
clk->index == R9A06G032_DIV_P2_PG) {
pr_devel("%s div uart hack!\n", __func__);
return clk_get_rate(hw->clk);
req->rate = clk_get_rate(hw->clk);
return 0;
}
req->rate = DIV_ROUND_UP(req->best_parent_rate, div);
pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk,
*prate, div, DIV_ROUND_UP(*prate, div));
return DIV_ROUND_UP(*prate, div);
req->best_parent_rate, div, req->rate);
return 0;
}
static int
@ -663,7 +664,7 @@ r9a06g032_div_set_rate(struct clk_hw *hw,
static const struct clk_ops r9a06g032_clk_div_ops = {
.recalc_rate = r9a06g032_div_recalc_rate,
.round_rate = r9a06g032_div_round_rate,
.determine_rate = r9a06g032_div_determine_rate,
.set_rate = r9a06g032_div_set_rate,
};

127
drivers/clk/renesas/r9a07g044-cpg.c Normal file
View File

@ -0,0 +1,127 @@
// SPDX-License-Identifier: GPL-2.0
/*
* RZ/G2L CPG driver
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <dt-bindings/clock/r9a07g044-cpg.h>
#include "renesas-rzg2l-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R9A07G044_OSCCLK,
/* External Input Clocks */
CLK_EXTAL,
/* Internal Core Clocks */
CLK_OSC_DIV1000,
CLK_PLL1,
CLK_PLL2,
CLK_PLL2_DIV2,
CLK_PLL2_DIV16,
CLK_PLL2_DIV20,
CLK_PLL3,
CLK_PLL3_DIV2,
CLK_PLL3_DIV4,
CLK_PLL3_DIV8,
CLK_PLL4,
CLK_PLL5,
CLK_PLL5_DIV2,
CLK_PLL6,
/* Module Clocks */
MOD_CLK_BASE,
};
/* Divider tables */
static const struct clk_div_table dtable_3b[] = {
{0, 1},
{1, 2},
{2, 4},
{3, 8},
{4, 32},
};
static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
/* Internal Core Clocks */
DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8),
/* Core output clk */
DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
dtable_3b, CLK_DIVIDER_HIWORD_MASK),
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK),
};
static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
DEF_MOD("gic", R9A07G044_CLK_GIC600,
R9A07G044_CLK_P1,
0x514, BIT(0), (BIT(0) | BIT(1))),
DEF_MOD("ia55", R9A07G044_CLK_IA55,
R9A07G044_CLK_P1,
0x518, (BIT(0) | BIT(1)), BIT(0)),
DEF_MOD("scif0", R9A07G044_CLK_SCIF0,
R9A07G044_CLK_P0,
0x584, BIT(0), BIT(0)),
DEF_MOD("scif1", R9A07G044_CLK_SCIF1,
R9A07G044_CLK_P0,
0x584, BIT(1), BIT(1)),
DEF_MOD("scif2", R9A07G044_CLK_SCIF2,
R9A07G044_CLK_P0,
0x584, BIT(2), BIT(2)),
DEF_MOD("scif3", R9A07G044_CLK_SCIF3,
R9A07G044_CLK_P0,
0x584, BIT(3), BIT(3)),
DEF_MOD("scif4", R9A07G044_CLK_SCIF4,
R9A07G044_CLK_P0,
0x584, BIT(4), BIT(4)),
DEF_MOD("sci0", R9A07G044_CLK_SCI0,
R9A07G044_CLK_P0,
0x588, BIT(0), BIT(0)),
};
static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A07G044_CLK_GIC600,
};
const struct rzg2l_cpg_info r9a07g044_cpg_info = {
/* Core Clocks */
.core_clks = r9a07g044_core_clks,
.num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Critical Module Clocks */
.crit_mod_clks = r9a07g044_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
/* Module Clocks */
.mod_clks = r9a07g044_mod_clks,
.num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
.num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1,
};

Some files were not shown because too many files have changed in this diff Show More