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SM501: Fix sm501_init_reg() mask/set order 

The order of the set and mask operation in sm501_init_reg() was setting and
then masking the bits set.  Correct the order so that we do not end up with
288MHz SDRAM clocks on certain systems.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Ben Dooks 2007-06-23 17:16:29 -07:00 committed by Linus Torvalds
parent b5913bbd2d
commit 5136237bc3
1 changed files with 4 additions and 1 deletions
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5
drivers/mfd/sm501.c
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@ -813,6 +813,9 @@ static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL);
/* sm501_init_reg
*
* Helper function for the init code to setup a register
*
* clear the bits which are set in r->mask, and then set
* the bits set in r->set.
*/
static inline void sm501_init_reg(struct sm501_devdata *sm,
@ -822,8 +825,8 @@ static inline void sm501_init_reg(struct sm501_devdata *sm,
unsigned long tmp;
tmp = readl(sm->regs + reg);
tmp |= r->set;
tmp &= ~r->mask;
tmp |= r->set;
writel(tmp, sm->regs + reg);
}