video: xilinxfb: Rename PLB_ACCESS_FLAG to BUS_ACCESS_FLAG
Using only PLB name is wrong for a long time because the same access functions are also used for AXI. s/PLB/BUS/g Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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@ -44,7 +44,7 @@
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/*
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/*
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* Xilinx calls it "PLB TFT LCD Controller" though it can also be used for
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* Xilinx calls it "TFT LCD Controller" though it can also be used for
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* the VGA port on the Xilinx ML40x board. This is a hardware display
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* the VGA port on the Xilinx ML40x board. This is a hardware display
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* controller for a 640x480 resolution TFT or VGA screen.
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* controller for a 640x480 resolution TFT or VGA screen.
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*
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*
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@ -54,11 +54,11 @@
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* don't start thinking about scrolling). The second allows the LCD to
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* don't start thinking about scrolling). The second allows the LCD to
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* be turned on or off as well as rotated 180 degrees.
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* be turned on or off as well as rotated 180 degrees.
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*
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*
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* In case of direct PLB access the second control register will be at
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* In case of direct BUS access the second control register will be at
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* an offset of 4 as compared to the DCR access where the offset is 1
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* an offset of 4 as compared to the DCR access where the offset is 1
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* i.e. REG_CTRL. So this is taken care in the function
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* i.e. REG_CTRL. So this is taken care in the function
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* xilinx_fb_out32 where it left shifts the offset 2 times in case of
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* xilinx_fb_out32 where it left shifts the offset 2 times in case of
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* direct PLB access.
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* direct BUS access.
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*/
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*/
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#define NUM_REGS 2
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#define NUM_REGS 2
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#define REG_FB_ADDR 0
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#define REG_FB_ADDR 0
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@ -116,7 +116,7 @@ static struct fb_var_screeninfo xilinx_fb_var = {
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};
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};
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#define PLB_ACCESS_FLAG 0x1 /* 1 = PLB, 0 = DCR */
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#define BUS_ACCESS_FLAG 0x1 /* 1 = BUS, 0 = DCR */
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struct xilinxfb_drvdata {
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struct xilinxfb_drvdata {
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@ -146,14 +146,14 @@ struct xilinxfb_drvdata {
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container_of(_info, struct xilinxfb_drvdata, info)
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container_of(_info, struct xilinxfb_drvdata, info)
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/*
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/*
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* The XPS TFT Controller can be accessed through PLB or DCR interface.
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* The XPS TFT Controller can be accessed through BUS or DCR interface.
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* To perform the read/write on the registers we need to check on
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* To perform the read/write on the registers we need to check on
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* which bus its connected and call the appropriate write API.
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* which bus its connected and call the appropriate write API.
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*/
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*/
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static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
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static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
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u32 val)
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u32 val)
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{
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{
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if (drvdata->flags & PLB_ACCESS_FLAG)
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if (drvdata->flags & BUS_ACCESS_FLAG)
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out_be32(drvdata->regs + (offset << 2), val);
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out_be32(drvdata->regs + (offset << 2), val);
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#ifdef CONFIG_PPC_DCR
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#ifdef CONFIG_PPC_DCR
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else
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else
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@ -235,10 +235,10 @@ static int xilinxfb_assign(struct device *dev,
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int rc;
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int rc;
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int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL;
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int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL;
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if (drvdata->flags & PLB_ACCESS_FLAG) {
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if (drvdata->flags & BUS_ACCESS_FLAG) {
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/*
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/*
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* Map the control registers in if the controller
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* Map the control registers in if the controller
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* is on direct PLB interface.
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* is on direct BUS interface.
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*/
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*/
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if (!request_mem_region(physaddr, 8, DRIVER_NAME)) {
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if (!request_mem_region(physaddr, 8, DRIVER_NAME)) {
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dev_err(dev, "Couldn't lock memory region at 0x%08lX\n",
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dev_err(dev, "Couldn't lock memory region at 0x%08lX\n",
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@ -270,7 +270,7 @@ static int xilinxfb_assign(struct device *dev,
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if (!drvdata->fb_virt) {
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if (!drvdata->fb_virt) {
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dev_err(dev, "Could not allocate frame buffer memory\n");
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dev_err(dev, "Could not allocate frame buffer memory\n");
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rc = -ENOMEM;
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rc = -ENOMEM;
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if (drvdata->flags & PLB_ACCESS_FLAG)
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if (drvdata->flags & BUS_ACCESS_FLAG)
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goto err_fbmem;
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goto err_fbmem;
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else
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else
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goto err_region;
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goto err_region;
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@ -323,7 +323,7 @@ static int xilinxfb_assign(struct device *dev,
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goto err_regfb;
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goto err_regfb;
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}
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}
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if (drvdata->flags & PLB_ACCESS_FLAG) {
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if (drvdata->flags & BUS_ACCESS_FLAG) {
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/* Put a banner in the log (for DEBUG) */
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/* Put a banner in the log (for DEBUG) */
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dev_dbg(dev, "regs: phys=%lx, virt=%p\n", physaddr,
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dev_dbg(dev, "regs: phys=%lx, virt=%p\n", physaddr,
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drvdata->regs);
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drvdata->regs);
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@ -348,11 +348,11 @@ err_cmap:
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xilinx_fb_out32(drvdata, REG_CTRL, 0);
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xilinx_fb_out32(drvdata, REG_CTRL, 0);
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err_fbmem:
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err_fbmem:
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if (drvdata->flags & PLB_ACCESS_FLAG)
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if (drvdata->flags & BUS_ACCESS_FLAG)
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iounmap(drvdata->regs);
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iounmap(drvdata->regs);
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err_map:
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err_map:
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if (drvdata->flags & PLB_ACCESS_FLAG)
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if (drvdata->flags & BUS_ACCESS_FLAG)
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release_mem_region(physaddr, 8);
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release_mem_region(physaddr, 8);
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err_region:
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err_region:
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@ -384,7 +384,7 @@ static int xilinxfb_release(struct device *dev)
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xilinx_fb_out32(drvdata, REG_CTRL, 0);
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xilinx_fb_out32(drvdata, REG_CTRL, 0);
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/* Release the resources, as allocated based on interface */
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/* Release the resources, as allocated based on interface */
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if (drvdata->flags & PLB_ACCESS_FLAG) {
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if (drvdata->flags & BUS_ACCESS_FLAG) {
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iounmap(drvdata->regs);
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iounmap(drvdata->regs);
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release_mem_region(drvdata->regs_phys, 8);
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release_mem_region(drvdata->regs_phys, 8);
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}
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}
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@ -423,18 +423,18 @@ static int xilinxfb_of_probe(struct platform_device *op)
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}
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}
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/*
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/*
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* To check whether the core is connected directly to DCR or PLB
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* To check whether the core is connected directly to DCR or BUS
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* interface and initialize the tft_access accordingly.
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* interface and initialize the tft_access accordingly.
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*/
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*/
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of_property_read_u32(op->dev.of_node, "xlnx,dcr-splb-slave-if",
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of_property_read_u32(op->dev.of_node, "xlnx,dcr-splb-slave-if",
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&tft_access);
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&tft_access);
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/*
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/*
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* Fill the resource structure if its direct PLB interface
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* Fill the resource structure if its direct BUS interface
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* otherwise fill the dcr_host structure.
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* otherwise fill the dcr_host structure.
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*/
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*/
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if (tft_access) {
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if (tft_access) {
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drvdata->flags |= PLB_ACCESS_FLAG;
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drvdata->flags |= BUS_ACCESS_FLAG;
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rc = of_address_to_resource(op->dev.of_node, 0, &res);
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rc = of_address_to_resource(op->dev.of_node, 0, &res);
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if (rc) {
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if (rc) {
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dev_err(&op->dev, "invalid address\n");
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dev_err(&op->dev, "invalid address\n");
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