ARM: OMAP36xx: remove clock36xx.c/.h files
These files contain legacy clock implementations which are no longer used for anything, thus remove them completely. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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@ -188,7 +188,7 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o
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obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
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obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
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obj-$(CONFIG_ARCH_OMAP3) += clock3517.o
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obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
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obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o
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@ -1,69 +0,0 @@
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/*
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* OMAP36xx-specific clkops
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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*
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* Mike Turquette
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* Vijaykumar GN
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* Paul Walmsley
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*
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* Parts of this code are based on code written by
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* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
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* Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include "clock.h"
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#include "clock36xx.h"
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#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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/**
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* omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
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* from HSDivider PWRDN problem Implements Errata ID: i556.
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* @clk: DPLL output struct clk
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*
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* 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
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* dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
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* valueafter their respective PWRDN bits are set. Any dummy write
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* (Any other value different from the Read value) to the
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* corresponding CM_CLKSEL register will refresh the dividers.
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*/
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int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
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{
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struct clk_divider *parent;
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struct clk_hw *parent_hw;
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u32 dummy_v, orig_v;
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struct clk_hw_omap *omap_clk = to_clk_hw_omap(clk);
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int ret;
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/* Clear PWRDN bit of HSDIVIDER */
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ret = omap2_dflt_clk_enable(clk);
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parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
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parent = to_clk_divider(parent_hw);
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/* Restore the dividers */
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if (!ret) {
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orig_v = omap2_clk_readl(omap_clk, parent->reg);
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dummy_v = orig_v;
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/* Write any other value different from the Read value */
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dummy_v ^= (1 << parent->shift);
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omap2_clk_writel(dummy_v, omap_clk, parent->reg);
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/* Write the original divider */
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omap2_clk_writel(orig_v, omap_clk, parent->reg);
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}
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return ret;
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}
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@ -1,13 +0,0 @@
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/*
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* OMAP36xx clock function prototypes and macros
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H
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extern int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *hw);
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#endif
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