can: m_can: fix whitespace in a few comments
Fixes whitespace in comments titling sections of register masks. Link: https://lore.kernel.org/r/20210504125123.500553-5-torin@maxiluxsystems.com Signed-off-by: Torin Cooper-Bennun <torin@maxiluxsystems.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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@ -101,7 +101,7 @@ enum m_can_reg {
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/* Test Register (TEST) */
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#define TEST_LBCK BIT(4)
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/* CC Control Register(CCCR) */
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/* CC Control Register (CCCR) */
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#define CCCR_TXP BIT(14)
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#define CCCR_TEST BIT(7)
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#define CCCR_DAR BIT(6)
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@ -147,18 +147,18 @@ enum m_can_reg {
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/* Timestamp Counter Value Register (TSCV) */
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#define TSCV_TSC_MASK GENMASK(15, 0)
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/* Error Counter Register(ECR) */
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/* Error Counter Register (ECR) */
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#define ECR_RP BIT(15)
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#define ECR_REC_MASK GENMASK(14, 8)
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#define ECR_TEC_MASK GENMASK(7, 0)
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/* Protocol Status Register(PSR) */
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/* Protocol Status Register (PSR) */
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#define PSR_BO BIT(7)
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#define PSR_EW BIT(6)
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#define PSR_EP BIT(5)
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#define PSR_LEC_MASK GENMASK(2, 0)
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/* Interrupt Register(IR) */
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/* Interrupt Register (IR) */
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#define IR_ALL_INT 0xffffffff
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/* Renamed bits for versions > 3.1.x */
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@ -250,7 +250,7 @@ enum m_can_reg {
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#define TXFQS_TFGI_MASK GENMASK(12, 8)
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#define TXFQS_TFFL_MASK GENMASK(5, 0)
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/* Tx Buffer Element Size Configuration(TXESC) */
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/* Tx Buffer Element Size Configuration (TXESC) */
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#define TXESC_TBDS_MASK GENMASK(2, 0)
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#define TXESC_TBDS_64B 0x7
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