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drm/i915: WaDisableRCCUnitClockGating isn't applicaple to VLV 

WaDisableRCCUnitClockGating is only relevant for SNB.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2014-01-22 21:32:49 +02:00 committed by Daniel Vetter
parent 28acf3b20c
commit 50eb3cf23c
1 changed files with 1 additions and 5 deletions
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6
drivers/gpu/drm/i915/intel_pm.c
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@ -4960,9 +4960,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
* Sanctuary and Tropics, and apparently anything else with * Sanctuary and Tropics, and apparently anything else with
* alpha test or pixel discard. * alpha test or pixel discard.
* *
* According to the spec, bit 11 (RCCUNIT) must also be set,
* but we didn't debug actual testcases to find it out.
*
* According to the spec, bit 13 (RCZUNIT) must be set on IVB. * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
* This implements the WaDisableRCZUnitClockGating:vlv workaround. * This implements the WaDisableRCZUnitClockGating:vlv workaround.
* *
@ -4973,8 +4970,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
GEN7_VDSUNIT_CLOCK_GATE_DISABLE | GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
GEN7_TDLUNIT_CLOCK_GATE_DISABLE | GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
GEN6_RCZUNIT_CLOCK_GATE_DISABLE | GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE);
GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
/* WaDisableL3Bank2xClockGate:vlv */ /* WaDisableL3Bank2xClockGate:vlv */
I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);