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clk: renesas: r7s9210: Add SDHI clocks 

Add SDHI clocks for RZ/A2

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Chris Brandt 2018-10-08 11:23:47 -05:00 committed by Geert Uytterhoeven
parent 651022382c
commit 507c93a22c
1 changed files with 5 additions and 0 deletions
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5
drivers/clk/renesas/r7s9210-cpg-mssr.c
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@ -98,6 +98,11 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
DEF_MOD_STB("spi2", 95, R7S9210_CLK_P1),
DEF_MOD_STB("spi1", 96, R7S9210_CLK_P1),
DEF_MOD_STB("spi0", 97, R7S9210_CLK_P1),
DEF_MOD_STB("sdhi11", 100, R7S9210_CLK_B),
DEF_MOD_STB("sdhi10", 101, R7S9210_CLK_B),
DEF_MOD_STB("sdhi01", 102, R7S9210_CLK_B),
DEF_MOD_STB("sdhi00", 103, R7S9210_CLK_B),
};
/* The clock dividers in the table vary based on DT and register settings */