[ALSA] soc - tlv320aic3x - revisit clock setup
This patch cleans up the clocking setup for aic3x codecs. It drops the dividers table and determines the PLL control values programatically. Under certain conditions, the PLL is disabled entirely which could save some power. Signed-off-by: Daniel Mack <daniel@caiaq.de> Acked-by: Jarkko Nikula <jarkko.nikula@nokia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
This commit is contained in:
Daniel Mack
Jaroslav Kysela
parent
bce7f793da
commit
4f9c16ccfa
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@ -49,7 +49,7 @@
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#include "tlv320aic3x.h"
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#define AUDIO_NAME "aic3x"
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#define AIC3X_VERSION "0.1"
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#define AIC3X_VERSION "0.2"
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/* codec private data */
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struct aic3x_priv {
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@ -648,81 +648,6 @@ static int aic3x_add_widgets(struct snd_soc_codec *codec)
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return 0;
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}
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struct aic3x_rate_divs {
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u32 mclk;
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u32 rate;
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u32 fsref_reg;
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u8 sr_reg:4;
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u8 pllj_reg;
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u16 plld_reg;
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};
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/* AIC3X codec mclk clock divider coefficients */
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static const struct aic3x_rate_divs aic3x_divs[] = {
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/* 8k */
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{12000000, 8000, 48000, 0xa, 16, 3840},
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{19200000, 8000, 48000, 0xa, 10, 2400},
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{22579200, 8000, 48000, 0xa, 8, 7075},
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{33868800, 8000, 48000, 0xa, 5, 8049},
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/* 11.025k */
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{12000000, 11025, 44100, 0x6, 15, 528},
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{19200000, 11025, 44100, 0x6, 9, 4080},
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{22579200, 11025, 44100, 0x6, 8, 0},
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{33868800, 11025, 44100, 0x6, 5, 3333},
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/* 16k */
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{12000000, 16000, 48000, 0x4, 16, 3840},
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{19200000, 16000, 48000, 0x4, 10, 2400},
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{22579200, 16000, 48000, 0x4, 8, 7075},
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{33868800, 16000, 48000, 0x4, 5, 8049},
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/* 22.05k */
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{12000000, 22050, 44100, 0x2, 15, 528},
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{19200000, 22050, 44100, 0x2, 9, 4080},
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{22579200, 22050, 44100, 0x2, 8, 0},
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{33868800, 22050, 44100, 0x2, 5, 3333},
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/* 32k */
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{12000000, 32000, 48000, 0x1, 16, 3840},
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{19200000, 32000, 48000, 0x1, 10, 2400},
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{22579200, 32000, 48000, 0x1, 8, 7075},
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{33868800, 32000, 48000, 0x1, 5, 8049},
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/* 44.1k */
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{12000000, 44100, 44100, 0x0, 15, 528},
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{19200000, 44100, 44100, 0x0, 9, 4080},
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{22579200, 44100, 44100, 0x0, 8, 0},
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{33868800, 44100, 44100, 0x0, 5, 3333},
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/* 48k */
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{12000000, 48000, 48000, 0x0, 16, 3840},
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{19200000, 48000, 48000, 0x0, 10, 2400},
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{22579200, 48000, 48000, 0x0, 8, 7075},
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{33868800, 48000, 48000, 0x0, 5, 8049},
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/* 64k */
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{12000000, 64000, 96000, 0x1, 16, 3840},
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{19200000, 64000, 96000, 0x1, 10, 2400},
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{22579200, 64000, 96000, 0x1, 8, 7075},
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{33868800, 64000, 96000, 0x1, 5, 8049},
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/* 88.2k */
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{12000000, 88200, 88200, 0x0, 15, 528},
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{19200000, 88200, 88200, 0x0, 9, 4080},
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{22579200, 88200, 88200, 0x0, 8, 0},
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{33868800, 88200, 88200, 0x0, 5, 3333},
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/* 96k */
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{12000000, 96000, 96000, 0x0, 16, 3840},
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{19200000, 96000, 96000, 0x0, 10, 2400},
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{22579200, 96000, 96000, 0x0, 8, 7075},
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{33868800, 96000, 96000, 0x0, 5, 8049},
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};
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static inline int aic3x_get_divs(int mclk, int rate)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(aic3x_divs); i++) {
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if (aic3x_divs[i].rate == rate && aic3x_divs[i].mclk == mclk)
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return i;
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}
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return 0;
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}
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static int aic3x_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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@ -730,57 +655,9 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
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struct snd_soc_device *socdev = rtd->socdev;
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struct snd_soc_codec *codec = socdev->codec;
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struct aic3x_priv *aic3x = codec->private_data;
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int i;
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u8 data, pll_p, pll_r, pll_j;
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u16 pll_d;
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i = aic3x_get_divs(aic3x->sysclk, params_rate(params));
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/* Route Left DAC to left channel input and
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* right DAC to right channel input */
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data = (LDAC2LCH | RDAC2RCH);
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switch (aic3x_divs[i].fsref_reg) {
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case 44100:
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data |= FSREF_44100;
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break;
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case 48000:
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data |= FSREF_48000;
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break;
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case 88200:
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data |= FSREF_44100 | DUAL_RATE_MODE;
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break;
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case 96000:
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data |= FSREF_48000 | DUAL_RATE_MODE;
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break;
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}
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aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
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/* codec sample rate select */
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data = aic3x_divs[i].sr_reg;
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data |= (data << 4);
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aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
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/* Use PLL for generation Fsref by equation:
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* Fsref = (MCLK * K * R)/(2048 * P);
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* Fix P = 2 and R = 1 and calculate K, if
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* K = J.D, i.e. J - an interger portion of K and D is the fractional
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* one with 4 digits of precision;
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* Example:
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* For MCLK = 22.5792 MHz and Fsref = 48kHz:
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* Select P = 2, R= 1, K = 8.7074, which results in J = 8, D = 7074
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*/
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pll_p = 2;
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pll_r = 1;
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pll_j = aic3x_divs[i].pllj_reg;
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pll_d = aic3x_divs[i].plld_reg;
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data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
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aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
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aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
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aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
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aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
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aic3x_write(codec, AIC3X_PLL_PROGD_REG,
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(pll_d & 0x3F) << PLLD_LSB_SHIFT);
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int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
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u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
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u16 pll_d = 1;
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/* select data word length */
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data =
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@ -800,6 +677,94 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
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}
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aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
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/* Fsref can be 44100 or 48000 */
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fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
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/* Try to find a value for Q which allows us to bypass the PLL and
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* generate CODEC_CLK directly. */
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for (pll_q = 2; pll_q < 18; pll_q++)
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if (aic3x->sysclk / (128 * pll_q) == fsref) {
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bypass_pll = 1;
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break;
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}
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if (bypass_pll) {
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pll_q &= 0xf;
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aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
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aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
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} else
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aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
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/* Route Left DAC to left channel input and
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* right DAC to right channel input */
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data = (LDAC2LCH | RDAC2RCH);
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data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
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if (params_rate(params) >= 64000)
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data |= DUAL_RATE_MODE;
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aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
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/* codec sample rate select */
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data = (fsref * 20) / params_rate(params);
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if (params_rate(params) < 64000)
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data /= 2;
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data /= 5;
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data -= 2;
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data |= (data << 4);
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aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
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if (bypass_pll)
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return 0;
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/* Use PLL
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* find an apropriate setup for j, d, r and p by iterating over
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* p and r - j and d are calculated for each fraction.
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* Up to 128 values are probed, the closest one wins the game.
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* The sysclk is divided by 1000 to prevent integer overflows.
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*/
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codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
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for (r = 1; r <= 16; r++)
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for (p = 1; p <= 8; p++) {
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int clk, tmp = (codec_clk * pll_r * 10) / pll_p;
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u8 j = tmp / 10000;
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u16 d = tmp % 10000;
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if (j > 63)
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continue;
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if (d != 0 && aic3x->sysclk < 10000000)
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continue;
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/* This is actually 1000 * ((j + (d/10000)) * r) / p
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* The term had to be converted to get rid of the
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* division by 10000 */
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clk = ((10000 * j * r) + (d * r)) / (10 * p);
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/* check whether this values get closer than the best
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* ones we had before */
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if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
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pll_j = j; pll_d = d; pll_r = r; pll_p = p;
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last_clk = clk;
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}
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/* Early exit for exact matches */
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if (clk == codec_clk)
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break;
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}
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if (last_clk == 0) {
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printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
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return -EINVAL;
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}
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data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
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aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
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aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
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aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
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aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
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aic3x_write(codec, AIC3X_PLL_PROGD_REG,
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(pll_d & 0x3F) << PLLD_LSB_SHIFT);
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return 0;
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}
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@ -826,16 +791,8 @@ static int aic3x_set_dai_sysclk(struct snd_soc_codec_dai *codec_dai,
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struct snd_soc_codec *codec = codec_dai->codec;
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struct aic3x_priv *aic3x = codec->private_data;
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switch (freq) {
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case 12000000:
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case 19200000:
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case 22579200:
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case 33868800:
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aic3x->sysclk = freq;
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return 0;
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}
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return -EINVAL;
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aic3x->sysclk = freq;
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return 0;
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}
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static int aic3x_set_dai_fmt(struct snd_soc_codec_dai *codec_dai,
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@ -109,6 +109,7 @@
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#define LLOPM_CTRL 86
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#define RLOPM_CTRL 93
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/* Clock generation control register */
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#define AIC3X_GPIOB_REG 101
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#define AIC3X_CLKGEN_CTRL_REG 102
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/* Page select register bits */
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@ -128,12 +129,15 @@
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/* PLL registers bitfields */
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#define PLLP_SHIFT 0
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#define PLLQ_SHIFT 3
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#define PLLR_SHIFT 0
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#define PLLJ_SHIFT 2
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#define PLLD_MSB_SHIFT 0
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#define PLLD_LSB_SHIFT 2
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/* Clock generation register bits */
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#define CODEC_CLKIN_PLLDIV 0
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#define CODEC_CLKIN_CLKDIV 1
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#define PLL_CLKIN_SHIFT 4
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#define MCLK_SOURCE 0x0
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#define PLL_CLKDIV_SHIFT 0
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