drm/amdgpu: more scheduler cleanups v2
Embed the scheduler into the ring structure instead of allocating it. Use the ring name directly instead of the id. v2: rebased, whitespace cleanup Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Chunming Zhou<david1.zhou@amd.com>
This commit is contained in:
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@ -433,7 +433,7 @@ int amdgpu_fence_driver_init(struct amdgpu_device *adev);
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void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
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void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
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void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
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int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
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int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
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struct amdgpu_irq_src *irq_src,
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unsigned irq_type);
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@ -891,7 +891,7 @@ struct amdgpu_ring {
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struct amdgpu_device *adev;
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const struct amdgpu_ring_funcs *funcs;
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struct amdgpu_fence_driver fence_drv;
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struct amd_gpu_scheduler *sched;
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struct amd_gpu_scheduler sched;
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spinlock_t fence_lock;
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struct mutex *ring_lock;
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@ -848,7 +848,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
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if (!job)
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return -ENOMEM;
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job->base.sched = ring->sched;
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job->base.sched = &ring->sched;
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job->base.s_entity = &parser->ctx->rings[ring->idx].entity;
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job->adev = parser->adev;
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job->ibs = parser->ibs;
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@ -43,10 +43,10 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
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for (i = 0; i < adev->num_rings; i++) {
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struct amd_sched_rq *rq;
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if (kernel)
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rq = &adev->rings[i]->sched->kernel_rq;
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rq = &adev->rings[i]->sched.kernel_rq;
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else
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rq = &adev->rings[i]->sched->sched_rq;
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r = amd_sched_entity_init(adev->rings[i]->sched,
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rq = &adev->rings[i]->sched.sched_rq;
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r = amd_sched_entity_init(&adev->rings[i]->sched,
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&ctx->rings[i].entity,
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rq, amdgpu_sched_jobs);
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if (r)
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@ -55,7 +55,7 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
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if (i < adev->num_rings) {
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for (j = 0; j < i; j++)
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amd_sched_entity_fini(adev->rings[j]->sched,
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amd_sched_entity_fini(&adev->rings[j]->sched,
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&ctx->rings[j].entity);
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kfree(ctx);
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return r;
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@ -75,7 +75,7 @@ void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
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if (amdgpu_enable_scheduler) {
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for (i = 0; i < adev->num_rings; i++)
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amd_sched_entity_fini(adev->rings[i]->sched,
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amd_sched_entity_fini(&adev->rings[i]->sched,
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&ctx->rings[i].entity);
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}
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}
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@ -609,9 +609,9 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
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* Init the fence driver for the requested ring (all asics).
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* Helper function for amdgpu_fence_driver_init().
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*/
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void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
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int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
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{
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int i;
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int i, r;
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ring->fence_drv.cpu_addr = NULL;
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ring->fence_drv.gpu_addr = 0;
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@ -628,14 +628,16 @@ void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
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init_waitqueue_head(&ring->fence_drv.fence_queue);
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if (amdgpu_enable_scheduler) {
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ring->sched = amd_sched_create(&amdgpu_sched_ops,
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ring->idx,
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amdgpu_sched_hw_submission,
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(void *)ring->adev);
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if (!ring->sched)
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DRM_ERROR("Failed to create scheduler on ring %d.\n",
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ring->idx);
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r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
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amdgpu_sched_hw_submission, ring->name);
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if (r) {
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DRM_ERROR("Failed to create scheduler on ring %s.\n",
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ring->name);
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return r;
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}
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}
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return 0;
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}
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/**
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@ -683,8 +685,7 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
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wake_up_all(&ring->fence_drv.fence_queue);
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amdgpu_irq_put(adev, ring->fence_drv.irq_src,
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ring->fence_drv.irq_type);
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if (ring->sched)
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amd_sched_destroy(ring->sched);
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amd_sched_fini(&ring->sched);
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ring->fence_drv.initialized = false;
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}
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mutex_unlock(&adev->ring_lock);
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@ -357,7 +357,9 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
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ring->adev = adev;
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ring->idx = adev->num_rings++;
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adev->rings[ring->idx] = ring;
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amdgpu_fence_driver_init_ring(ring);
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r = amdgpu_fence_driver_init_ring(ring);
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if (r)
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return r;
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}
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r = amdgpu_wb_get(adev, &ring->rptr_offs);
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@ -145,8 +145,13 @@ static uint32_t amdgpu_sa_get_ring_from_fence(struct fence *f)
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struct amd_sched_fence *s_fence;
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s_fence = to_amd_sched_fence(f);
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if (s_fence)
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return s_fence->sched->ring_id;
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if (s_fence) {
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struct amdgpu_ring *ring;
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ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
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return ring->idx;
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}
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a_fence = to_amdgpu_fence(f);
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if (a_fence)
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return a_fence->ring->idx;
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@ -412,6 +417,26 @@ void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo,
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}
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#if defined(CONFIG_DEBUG_FS)
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static void amdgpu_sa_bo_dump_fence(struct fence *fence, struct seq_file *m)
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{
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struct amdgpu_fence *a_fence = to_amdgpu_fence(fence);
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struct amd_sched_fence *s_fence = to_amd_sched_fence(fence);
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if (a_fence)
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seq_printf(m, " protected by 0x%016llx on ring %d",
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a_fence->seq, a_fence->ring->idx);
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if (s_fence) {
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struct amdgpu_ring *ring;
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ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
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seq_printf(m, " protected by 0x%016x on ring %d",
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s_fence->base.seqno, ring->idx);
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}
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}
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void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
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struct seq_file *m)
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{
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@ -428,18 +453,8 @@ void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
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}
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seq_printf(m, "[0x%010llx 0x%010llx] size %8lld",
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soffset, eoffset, eoffset - soffset);
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if (i->fence) {
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struct amdgpu_fence *a_fence = to_amdgpu_fence(i->fence);
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struct amd_sched_fence *s_fence = to_amd_sched_fence(i->fence);
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if (a_fence)
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seq_printf(m, " protected by 0x%016llx on ring %d",
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a_fence->seq, a_fence->ring->idx);
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if (s_fence)
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seq_printf(m, " protected by 0x%016x on ring %d",
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s_fence->base.seqno,
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s_fence->sched->ring_id);
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}
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if (i->fence)
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amdgpu_sa_bo_dump_fence(i->fence, m);
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seq_printf(m, "\n");
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}
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spin_unlock(&sa_manager->wq.lock);
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@ -85,7 +85,7 @@ int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
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kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
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if (!job)
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return -ENOMEM;
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job->base.sched = ring->sched;
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job->base.sched = &ring->sched;
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job->base.s_entity = &adev->kernel_ctx.rings[ring->idx].entity;
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job->adev = adev;
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job->ibs = ibs;
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@ -65,8 +65,14 @@ static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f)
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if (a_fence)
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return a_fence->ring->adev == adev;
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if (s_fence)
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return (struct amdgpu_device *)s_fence->sched->priv == adev;
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if (s_fence) {
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struct amdgpu_ring *ring;
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ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
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return ring->adev == adev;
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}
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return false;
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}
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@ -16,21 +16,21 @@ TRACE_EVENT(amd_sched_job,
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TP_ARGS(sched_job),
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TP_STRUCT__entry(
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__field(struct amd_sched_entity *, entity)
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__field(u32, ring_id)
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__field(const char *, name)
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__field(u32, job_count)
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__field(int, hw_job_count)
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),
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TP_fast_assign(
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__entry->entity = sched_job->s_entity;
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__entry->ring_id = sched_job->sched->ring_id;
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__entry->name = sched_job->sched->name;
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__entry->job_count = kfifo_len(
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&sched_job->s_entity->job_queue) / sizeof(sched_job);
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__entry->hw_job_count = atomic_read(
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&sched_job->sched->hw_rq_count);
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),
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TP_printk("entity=%p, ring=%u, job count:%u, hw job count:%d",
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__entry->entity, __entry->ring_id, __entry->job_count,
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TP_printk("entity=%p, ring=%s, job count:%u, hw job count:%d",
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__entry->entity, __entry->name, __entry->job_count,
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__entry->hw_job_count)
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);
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#endif
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@ -381,56 +381,45 @@ static int amd_sched_main(void *param)
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}
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/**
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* Create a gpu scheduler
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* Init a gpu scheduler instance
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*
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* @sched The pointer to the scheduler
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* @ops The backend operations for this scheduler.
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* @ring The the ring id for the scheduler.
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* @hw_submissions Number of hw submissions to do.
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* @name Name used for debugging
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*
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* Return the pointer to scheduler for success, otherwise return NULL
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* Return 0 on success, otherwise error code.
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*/
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struct amd_gpu_scheduler *amd_sched_create(struct amd_sched_backend_ops *ops,
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unsigned ring, unsigned hw_submission,
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void *priv)
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int amd_sched_init(struct amd_gpu_scheduler *sched,
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struct amd_sched_backend_ops *ops,
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unsigned hw_submission, const char *name)
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{
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struct amd_gpu_scheduler *sched;
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sched = kzalloc(sizeof(struct amd_gpu_scheduler), GFP_KERNEL);
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if (!sched)
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return NULL;
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sched->ops = ops;
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sched->ring_id = ring;
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sched->hw_submission_limit = hw_submission;
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sched->priv = priv;
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snprintf(sched->name, sizeof(sched->name), "amdgpu[%d]", ring);
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sched->name = name;
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amd_sched_rq_init(&sched->sched_rq);
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amd_sched_rq_init(&sched->kernel_rq);
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init_waitqueue_head(&sched->wake_up_worker);
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init_waitqueue_head(&sched->job_scheduled);
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atomic_set(&sched->hw_rq_count, 0);
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/* Each scheduler will run on a seperate kernel thread */
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sched->thread = kthread_run(amd_sched_main, sched, sched->name);
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if (IS_ERR(sched->thread)) {
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DRM_ERROR("Failed to create scheduler for id %d.\n", ring);
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kfree(sched);
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return NULL;
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DRM_ERROR("Failed to create scheduler for %s.\n", name);
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return PTR_ERR(sched->thread);
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}
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return sched;
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return 0;
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}
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/**
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* Destroy a gpu scheduler
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*
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* @sched The pointer to the scheduler
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*
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* return 0 if succeed. -1 if failed.
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*/
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int amd_sched_destroy(struct amd_gpu_scheduler *sched)
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void amd_sched_fini(struct amd_gpu_scheduler *sched)
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{
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kthread_stop(sched->thread);
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kfree(sched);
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return 0;
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}
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@ -101,23 +101,21 @@ struct amd_sched_backend_ops {
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* One scheduler is implemented for each hardware ring
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*/
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struct amd_gpu_scheduler {
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struct task_struct *thread;
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struct amd_sched_backend_ops *ops;
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uint32_t hw_submission_limit;
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const char *name;
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struct amd_sched_rq sched_rq;
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struct amd_sched_rq kernel_rq;
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atomic_t hw_rq_count;
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struct amd_sched_backend_ops *ops;
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uint32_t ring_id;
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wait_queue_head_t wake_up_worker;
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wait_queue_head_t job_scheduled;
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uint32_t hw_submission_limit;
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char name[20];
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void *priv;
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atomic_t hw_rq_count;
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struct task_struct *thread;
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};
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struct amd_gpu_scheduler *
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amd_sched_create(struct amd_sched_backend_ops *ops,
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uint32_t ring, uint32_t hw_submission, void *priv);
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int amd_sched_destroy(struct amd_gpu_scheduler *sched);
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int amd_sched_init(struct amd_gpu_scheduler *sched,
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struct amd_sched_backend_ops *ops,
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uint32_t hw_submission, const char *name);
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void amd_sched_fini(struct amd_gpu_scheduler *sched);
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int amd_sched_entity_init(struct amd_gpu_scheduler *sched,
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struct amd_sched_entity *entity,
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