iwlwifi: move txq-specific from trans_pcie to common trans
We don't want to have txq code in the PCIe transport code, so move all the relevant elements to a new iwl_txq structure and store it in iwl_trans. spatch @ replace_pcie @ struct iwl_trans_pcie *trans_pcie; @@ ( -trans_pcie->queue_stopped +trans->txqs.queue_stopped | -trans_pcie->queue_used +trans->txqs.queue_used | -trans_pcie->txq +trans->txqs.txq | -trans_pcie->txq +trans->txqs.txq | -trans_pcie->cmd_queue +trans->txqs.cmd.q_id | -trans_pcie->cmd_fifo +trans->txqs.cmd.fifo | -trans_pcie->cmd_q_wdg_timeout +trans->txqs.cmd.wdg_timeout ) // clean all new unused variables @ depends on replace_pcie @ type T; identifier i; expression E; @@ - T i = E; ... when != i Signed-off-by: Mordechay Goodstein <mordechay.goodstein@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/iwlwifi.20200529092401.a428d3c9d66f.Ie04ae55f33954636a39c98e7ae1e739c0507435b@changeid
This commit is contained in:
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@ -902,6 +902,25 @@ struct iwl_txq {
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bool overflow_tx;
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};
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/**
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* struct iwl_trans_txqs - transport tx queues data
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*
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* @queue_used - bit mask of used queues
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* @queue_stopped - bit mask of stopped queues
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*/
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struct iwl_trans_txqs {
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unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
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unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
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struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES];
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struct {
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u8 fifo;
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u8 q_id;
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unsigned int wdg_timeout;
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} cmd;
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};
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/**
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* struct iwl_trans - transport common data
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*
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@ -935,6 +954,7 @@ struct iwl_txq {
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* @system_pm_mode: the system-wide power management mode in use.
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* This mode is set dynamically, depending on the WoWLAN values
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* configured from the userspace at runtime.
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* @iwl_trans_txqs: transport tx queues data.
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*/
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struct iwl_trans {
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const struct iwl_trans_ops *ops;
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@ -982,6 +1002,7 @@ struct iwl_trans {
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enum iwl_plat_pm_mode system_pm_mode;
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const char *name;
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struct iwl_trans_txqs txqs;
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/* pointer to trans specific struct */
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/*Ensure that this pointer will always be aligned to sizeof pointer */
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@ -221,7 +221,7 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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ctxt_info_gen3->tr_idx_arr_size =
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cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS);
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ctxt_info_gen3->mtr_base_addr =
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cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr);
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cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr);
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ctxt_info_gen3->mcr_base_addr =
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cpu_to_le64(trans_pcie->rxq->used_bd_dma);
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ctxt_info_gen3->mtr_size =
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@ -6,7 +6,7 @@
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 - 2019 Intel Corporation
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* Copyright(c) 2018 - 2020 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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@ -20,7 +20,7 @@
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* BSD LICENSE
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 - 2019 Intel Corporation
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* Copyright(c) 2018 - 2020 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -263,7 +263,7 @@ int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
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/* initialize TX command queue */
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ctxt_info->hcmd_cfg.cmd_queue_addr =
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cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr);
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cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr);
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ctxt_info->hcmd_cfg.cmd_queue_size =
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TFD_QUEUE_CB_SIZE(IWL_CMD_QUEUE_SIZE);
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@ -454,9 +454,6 @@ struct iwl_trans_pcie {
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struct dma_pool *bc_pool;
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struct iwl_txq *txq_memory;
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struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES];
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unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
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unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
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/* PCI bus related data */
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struct pci_dev *pci_dev;
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@ -470,10 +467,7 @@ struct iwl_trans_pcie {
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u8 page_offs, dev_cmd_offs;
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u8 cmd_queue;
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u8 def_rx_queue;
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u8 cmd_fifo;
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unsigned int cmd_q_wdg_timeout;
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u8 n_no_reclaim_cmds;
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u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
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u8 max_tbs;
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@ -876,9 +870,7 @@ void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans);
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static inline void iwl_wake_queue(struct iwl_trans *trans,
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struct iwl_txq *txq)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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if (test_and_clear_bit(txq->id, trans_pcie->queue_stopped)) {
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if (test_and_clear_bit(txq->id, trans->txqs.queue_stopped)) {
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IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id);
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iwl_op_mode_queue_not_full(trans->op_mode, txq->id);
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}
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@ -887,9 +879,7 @@ static inline void iwl_wake_queue(struct iwl_trans *trans,
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static inline void iwl_stop_queue(struct iwl_trans *trans,
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struct iwl_txq *txq)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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if (!test_and_set_bit(txq->id, trans_pcie->queue_stopped)) {
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if (!test_and_set_bit(txq->id, trans->txqs.queue_stopped)) {
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iwl_op_mode_queue_full(trans->op_mode, txq->id);
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IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id);
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} else
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@ -1284,7 +1284,7 @@ static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
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int i)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
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struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id];
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bool page_stolen = false;
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int max_len = trans_pcie->rx_buf_bytes;
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u32 offset = 0;
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@ -1671,9 +1671,9 @@ static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
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}
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for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
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if (!trans_pcie->txq[i])
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if (!trans->txqs.txq[i])
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continue;
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del_timer(&trans_pcie->txq[i]->stuck_timer);
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del_timer(&trans->txqs.txq[i]->stuck_timer);
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}
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/* The STATUS_FW_ERROR bit is set in this function. This must happen
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@ -6,7 +6,7 @@
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 - 2019 Intel Corporation
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* Copyright(c) 2018 - 2020 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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@ -20,7 +20,7 @@
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* BSD LICENSE
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 - 2019 Intel Corporation
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* Copyright(c) 2018 - 2020 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -245,7 +245,7 @@ static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
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return -ENOMEM;
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/* Allocate or reset and init all Tx and Command queues */
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if (iwl_pcie_gen2_tx_init(trans, trans_pcie->cmd_queue, queue_size))
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if (iwl_pcie_gen2_tx_init(trans, trans->txqs.cmd.q_id, queue_size))
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return -ENOMEM;
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/* enable shadow regs in HW */
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@ -262,8 +262,9 @@ void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr)
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iwl_pcie_reset_ict(trans);
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/* make sure all queue are not stopped/used */
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memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
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memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
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memset(trans->txqs.queue_stopped, 0,
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sizeof(trans->txqs.queue_stopped));
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memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
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/* now that we got alive we can free the fw image & the context info.
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* paging memory cannot be freed included since FW will still use it
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@ -1904,9 +1904,9 @@ static void iwl_trans_pcie_configure(struct iwl_trans *trans,
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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trans_pcie->cmd_queue = trans_cfg->cmd_queue;
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trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
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trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
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trans->txqs.cmd.q_id = trans_cfg->cmd_queue;
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trans->txqs.cmd.fifo = trans_cfg->cmd_fifo;
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trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
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if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
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trans_pcie->n_no_reclaim_cmds = 0;
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else
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@ -2199,11 +2199,10 @@ static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
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unsigned long txqs,
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bool freeze)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int queue;
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for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
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struct iwl_txq *txq = trans_pcie->txq[queue];
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struct iwl_txq *txq = trans->txqs.txq[queue];
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unsigned long now;
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spin_lock_bh(&txq->lock);
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@ -2251,13 +2250,12 @@ next_queue:
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static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int i;
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for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
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struct iwl_txq *txq = trans_pcie->txq[i];
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struct iwl_txq *txq = trans->txqs.txq[i];
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if (i == trans_pcie->cmd_queue)
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if (i == trans->txqs.cmd.q_id)
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continue;
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spin_lock_bh(&txq->lock);
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@ -2326,7 +2324,6 @@ static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
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static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_txq *txq;
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unsigned long now = jiffies;
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bool overflow_tx;
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@ -2336,11 +2333,11 @@ static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
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if (test_bit(STATUS_TRANS_DEAD, &trans->status))
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return -ENODEV;
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if (!test_bit(txq_idx, trans_pcie->queue_used))
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if (!test_bit(txq_idx, trans->txqs.queue_used))
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return -EINVAL;
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IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
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txq = trans_pcie->txq[txq_idx];
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txq = trans->txqs.txq[txq_idx];
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spin_lock_bh(&txq->lock);
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overflow_tx = txq->overflow_tx ||
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@ -2388,7 +2385,6 @@ static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
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static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int cnt;
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int ret = 0;
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@ -2397,9 +2393,9 @@ static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
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cnt < trans->trans_cfg->base_params->num_of_queues;
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cnt++) {
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if (cnt == trans_pcie->cmd_queue)
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if (cnt == trans->txqs.cmd.q_id)
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continue;
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if (!test_bit(cnt, trans_pcie->queue_used))
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if (!test_bit(cnt, trans->txqs.queue_used))
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continue;
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if (!(BIT(cnt) & txq_bm))
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continue;
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@ -2573,13 +2569,12 @@ static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
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struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
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struct iwl_dbgfs_tx_queue_state *state = v;
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struct iwl_trans *trans = priv->trans;
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_txq *txq = trans_pcie->txq[state->pos];
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struct iwl_txq *txq = trans->txqs.txq[state->pos];
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seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",
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(unsigned int)state->pos,
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!!test_bit(state->pos, trans_pcie->queue_used),
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!!test_bit(state->pos, trans_pcie->queue_stopped));
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!!test_bit(state->pos, trans->txqs.queue_used),
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!!test_bit(state->pos, trans->txqs.queue_stopped));
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if (txq)
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seq_printf(seq,
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"read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
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@ -2589,7 +2584,7 @@ static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
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else
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seq_puts(seq, "(unallocated)");
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if (state->pos == trans_pcie->cmd_queue)
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if (state->pos == trans->txqs.cmd.q_id)
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seq_puts(seq, " (HCMD)");
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seq_puts(seq, "\n");
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@ -3265,7 +3260,7 @@ static struct iwl_trans_dump_data
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_fw_error_dump_data *data;
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struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
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struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id];
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struct iwl_fw_error_dump_txcmd *txcmd;
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struct iwl_trans_dump_data *dump_data;
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u32 len, num_rbs = 0, monitor_len = 0;
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@ -64,7 +64,6 @@
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*/
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void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int txq_id;
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/*
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@ -72,12 +71,13 @@ void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans)
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* queues. This happens when we have an rfkill interrupt.
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* Since we stop Tx altogether - mark the queues as stopped.
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*/
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memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
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memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
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memset(trans->txqs.queue_stopped, 0,
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sizeof(trans->txqs.queue_stopped));
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memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
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/* Unmap DMA from host system and free skb's */
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for (txq_id = 0; txq_id < ARRAY_SIZE(trans_pcie->txq); txq_id++) {
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if (!trans_pcie->txq[txq_id])
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for (txq_id = 0; txq_id < ARRAY_SIZE(trans->txqs.txq); txq_id++) {
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if (!trans->txqs.txq[txq_id])
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continue;
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iwl_pcie_gen2_txq_unmap(trans, txq_id);
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}
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@ -716,7 +716,7 @@ int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_cmd_meta *out_meta;
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struct iwl_txq *txq = trans_pcie->txq[txq_id];
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struct iwl_txq *txq = trans->txqs.txq[txq_id];
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u16 cmd_len;
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int idx;
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void *tfd;
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@ -725,7 +725,7 @@ int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
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"queue %d out of range", txq_id))
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return -EINVAL;
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if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
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if (WARN_ONCE(!test_bit(txq_id, trans->txqs.queue_used),
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"TX on unused queue %d\n", txq_id))
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return -EINVAL;
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||||
|
@ -819,7 +819,7 @@ static int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
|
|||
struct iwl_host_cmd *cmd)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
|
||||
struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id];
|
||||
struct iwl_device_cmd *out_cmd;
|
||||
struct iwl_cmd_meta *out_meta;
|
||||
unsigned long flags;
|
||||
|
@ -931,7 +931,7 @@ static int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
|
|||
cpu_to_le16(cmd_size - sizeof(struct iwl_cmd_header_wide));
|
||||
out_cmd->hdr_wide.reserved = 0;
|
||||
out_cmd->hdr_wide.sequence =
|
||||
cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
|
||||
cpu_to_le16(QUEUE_TO_SEQ(trans->txqs.cmd.q_id) |
|
||||
INDEX_TO_SEQ(txq->write_ptr));
|
||||
|
||||
cmd_pos = sizeof(struct iwl_cmd_header_wide);
|
||||
|
@ -979,7 +979,7 @@ static int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
|
|||
"Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
|
||||
iwl_get_cmd_string(trans, cmd->id), group_id,
|
||||
out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
|
||||
cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
|
||||
cmd_size, txq->write_ptr, idx, trans->txqs.cmd.q_id);
|
||||
|
||||
/* start the TFD with the minimum copy bytes */
|
||||
tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
|
||||
|
@ -1056,7 +1056,7 @@ static int iwl_pcie_gen2_send_hcmd_sync(struct iwl_trans *trans,
|
|||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
const char *cmd_str = iwl_get_cmd_string(trans, cmd->id);
|
||||
struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
|
||||
struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id];
|
||||
int cmd_idx;
|
||||
int ret;
|
||||
|
||||
|
@ -1175,14 +1175,14 @@ int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
|
|||
void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *txq = trans_pcie->txq[txq_id];
|
||||
struct iwl_txq *txq = trans->txqs.txq[txq_id];
|
||||
|
||||
spin_lock_bh(&txq->lock);
|
||||
while (txq->write_ptr != txq->read_ptr) {
|
||||
IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
|
||||
txq_id, txq->read_ptr);
|
||||
|
||||
if (txq_id != trans_pcie->cmd_queue) {
|
||||
if (txq_id != trans->txqs.cmd.q_id) {
|
||||
int idx = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
|
||||
struct sk_buff *skb = txq->entries[idx].skb;
|
||||
|
||||
|
@ -1240,7 +1240,6 @@ void iwl_pcie_gen2_txq_free_memory(struct iwl_trans *trans,
|
|||
*/
|
||||
static void iwl_pcie_gen2_txq_free(struct iwl_trans *trans, int txq_id)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *txq;
|
||||
int i;
|
||||
|
||||
|
@ -1248,7 +1247,7 @@ static void iwl_pcie_gen2_txq_free(struct iwl_trans *trans, int txq_id)
|
|||
"queue %d out of range", txq_id))
|
||||
return;
|
||||
|
||||
txq = trans_pcie->txq[txq_id];
|
||||
txq = trans->txqs.txq[txq_id];
|
||||
|
||||
if (WARN_ON(!txq))
|
||||
return;
|
||||
|
@ -1256,7 +1255,7 @@ static void iwl_pcie_gen2_txq_free(struct iwl_trans *trans, int txq_id)
|
|||
iwl_pcie_gen2_txq_unmap(trans, txq_id);
|
||||
|
||||
/* De-alloc array of command/tx buffers */
|
||||
if (txq_id == trans_pcie->cmd_queue)
|
||||
if (txq_id == trans->txqs.cmd.q_id)
|
||||
for (i = 0; i < txq->n_window; i++) {
|
||||
kzfree(txq->entries[i].cmd);
|
||||
kzfree(txq->entries[i].free_buf);
|
||||
|
@ -1265,9 +1264,9 @@ static void iwl_pcie_gen2_txq_free(struct iwl_trans *trans, int txq_id)
|
|||
|
||||
iwl_pcie_gen2_txq_free_memory(trans, txq);
|
||||
|
||||
trans_pcie->txq[txq_id] = NULL;
|
||||
trans->txqs.txq[txq_id] = NULL;
|
||||
|
||||
clear_bit(txq_id, trans_pcie->queue_used);
|
||||
clear_bit(txq_id, trans->txqs.queue_used);
|
||||
}
|
||||
|
||||
int iwl_trans_pcie_dyn_txq_alloc_dma(struct iwl_trans *trans,
|
||||
|
@ -1327,7 +1326,6 @@ int iwl_trans_pcie_txq_alloc_response(struct iwl_trans *trans,
|
|||
struct iwl_txq *txq,
|
||||
struct iwl_host_cmd *hcmd)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_tx_queue_cfg_rsp *rsp;
|
||||
int ret, qid;
|
||||
u32 wr_ptr;
|
||||
|
@ -1342,20 +1340,20 @@ int iwl_trans_pcie_txq_alloc_response(struct iwl_trans *trans,
|
|||
qid = le16_to_cpu(rsp->queue_number);
|
||||
wr_ptr = le16_to_cpu(rsp->write_pointer);
|
||||
|
||||
if (qid >= ARRAY_SIZE(trans_pcie->txq)) {
|
||||
if (qid >= ARRAY_SIZE(trans->txqs.txq)) {
|
||||
WARN_ONCE(1, "queue index %d unsupported", qid);
|
||||
ret = -EIO;
|
||||
goto error_free_resp;
|
||||
}
|
||||
|
||||
if (test_and_set_bit(qid, trans_pcie->queue_used)) {
|
||||
if (test_and_set_bit(qid, trans->txqs.queue_used)) {
|
||||
WARN_ONCE(1, "queue %d already used", qid);
|
||||
ret = -EIO;
|
||||
goto error_free_resp;
|
||||
}
|
||||
|
||||
txq->id = qid;
|
||||
trans_pcie->txq[qid] = txq;
|
||||
trans->txqs.txq[qid] = txq;
|
||||
wr_ptr &= (trans->trans_cfg->base_params->max_tfd_queue_size - 1);
|
||||
|
||||
/* Place first TFD at index corresponding to start sequence number */
|
||||
|
@ -1413,8 +1411,6 @@ error:
|
|||
|
||||
void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
|
||||
if (WARN(queue >= IWL_MAX_TVQM_QUEUES,
|
||||
"queue %d out of range", queue))
|
||||
return;
|
||||
|
@ -1425,7 +1421,7 @@ void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue)
|
|||
* allow the op_mode to call txq_disable after it already called
|
||||
* stop_device.
|
||||
*/
|
||||
if (!test_and_clear_bit(queue, trans_pcie->queue_used)) {
|
||||
if (!test_and_clear_bit(queue, trans->txqs.queue_used)) {
|
||||
WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
|
||||
"queue %d not used", queue);
|
||||
return;
|
||||
|
@ -1433,22 +1429,21 @@ void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue)
|
|||
|
||||
iwl_pcie_gen2_txq_unmap(trans, queue);
|
||||
|
||||
iwl_pcie_gen2_txq_free_memory(trans, trans_pcie->txq[queue]);
|
||||
trans_pcie->txq[queue] = NULL;
|
||||
iwl_pcie_gen2_txq_free_memory(trans, trans->txqs.txq[queue]);
|
||||
trans->txqs.txq[queue] = NULL;
|
||||
|
||||
IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", queue);
|
||||
}
|
||||
|
||||
void iwl_pcie_gen2_tx_free(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
int i;
|
||||
|
||||
memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
|
||||
memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
|
||||
|
||||
/* Free all TX queues */
|
||||
for (i = 0; i < ARRAY_SIZE(trans_pcie->txq); i++) {
|
||||
if (!trans_pcie->txq[i])
|
||||
for (i = 0; i < ARRAY_SIZE(trans->txqs.txq); i++) {
|
||||
if (!trans->txqs.txq[i])
|
||||
continue;
|
||||
|
||||
iwl_pcie_gen2_txq_free(trans, i);
|
||||
|
@ -1457,35 +1452,34 @@ void iwl_pcie_gen2_tx_free(struct iwl_trans *trans)
|
|||
|
||||
int iwl_pcie_gen2_tx_init(struct iwl_trans *trans, int txq_id, int queue_size)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *queue;
|
||||
int ret;
|
||||
|
||||
/* alloc and init the tx queue */
|
||||
if (!trans_pcie->txq[txq_id]) {
|
||||
if (!trans->txqs.txq[txq_id]) {
|
||||
queue = kzalloc(sizeof(*queue), GFP_KERNEL);
|
||||
if (!queue) {
|
||||
IWL_ERR(trans, "Not enough memory for tx queue\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
trans_pcie->txq[txq_id] = queue;
|
||||
trans->txqs.txq[txq_id] = queue;
|
||||
ret = iwl_pcie_txq_alloc(trans, queue, queue_size, true);
|
||||
if (ret) {
|
||||
IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
|
||||
goto error;
|
||||
}
|
||||
} else {
|
||||
queue = trans_pcie->txq[txq_id];
|
||||
queue = trans->txqs.txq[txq_id];
|
||||
}
|
||||
|
||||
ret = iwl_pcie_txq_init(trans, queue, queue_size,
|
||||
(txq_id == trans_pcie->cmd_queue));
|
||||
(txq_id == trans->txqs.cmd.q_id));
|
||||
if (ret) {
|
||||
IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
|
||||
goto error;
|
||||
}
|
||||
trans_pcie->txq[txq_id]->id = txq_id;
|
||||
set_bit(txq_id, trans_pcie->queue_used);
|
||||
trans->txqs.txq[txq_id]->id = txq_id;
|
||||
set_bit(txq_id, trans->txqs.queue_used);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
@ -261,7 +261,7 @@ static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
|
|||
|
||||
WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
|
||||
|
||||
if (txq_id != trans_pcie->cmd_queue)
|
||||
if (txq_id != trans->txqs.cmd.q_id)
|
||||
sta_id = tx_cmd->sta_id;
|
||||
|
||||
bc_ent = cpu_to_le16(1 | (sta_id << 12));
|
||||
|
@ -279,7 +279,6 @@ static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
|
|||
static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
|
||||
struct iwl_txq *txq)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
u32 reg = 0;
|
||||
int txq_id = txq->id;
|
||||
|
||||
|
@ -292,7 +291,7 @@ static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
|
|||
* 3. there is a chance that the NIC is asleep
|
||||
*/
|
||||
if (!trans->trans_cfg->base_params->shadow_reg_enable &&
|
||||
txq_id != trans_pcie->cmd_queue &&
|
||||
txq_id != trans->txqs.cmd.q_id &&
|
||||
test_bit(STATUS_TPOWER_PMI, &trans->status)) {
|
||||
/*
|
||||
* wake up nic if it's powered down ...
|
||||
|
@ -323,13 +322,12 @@ static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
|
|||
|
||||
void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
|
||||
struct iwl_txq *txq = trans_pcie->txq[i];
|
||||
struct iwl_txq *txq = trans->txqs.txq[i];
|
||||
|
||||
if (!test_bit(i, trans_pcie->queue_used))
|
||||
if (!test_bit(i, trans->txqs.queue_used))
|
||||
continue;
|
||||
|
||||
spin_lock_bh(&txq->lock);
|
||||
|
@ -660,14 +658,14 @@ static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
|
|||
static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *txq = trans_pcie->txq[txq_id];
|
||||
struct iwl_txq *txq = trans->txqs.txq[txq_id];
|
||||
|
||||
spin_lock_bh(&txq->lock);
|
||||
while (txq->write_ptr != txq->read_ptr) {
|
||||
IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
|
||||
txq_id, txq->read_ptr);
|
||||
|
||||
if (txq_id != trans_pcie->cmd_queue) {
|
||||
if (txq_id != trans->txqs.cmd.q_id) {
|
||||
struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
|
||||
|
||||
if (WARN_ON_ONCE(!skb))
|
||||
|
@ -682,7 +680,7 @@ static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
|
|||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&trans_pcie->reg_lock, flags);
|
||||
if (txq_id == trans_pcie->cmd_queue)
|
||||
if (txq_id == trans->txqs.cmd.q_id)
|
||||
iwl_pcie_clear_cmd_in_flight(trans);
|
||||
spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
|
||||
}
|
||||
|
@ -711,7 +709,7 @@ static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
|
|||
static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *txq = trans_pcie->txq[txq_id];
|
||||
struct iwl_txq *txq = trans->txqs.txq[txq_id];
|
||||
struct device *dev = trans->dev;
|
||||
int i;
|
||||
|
||||
|
@ -721,7 +719,7 @@ static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
|
|||
iwl_pcie_txq_unmap(trans, txq_id);
|
||||
|
||||
/* De-alloc array of command/tx buffers */
|
||||
if (txq_id == trans_pcie->cmd_queue)
|
||||
if (txq_id == trans->txqs.cmd.q_id)
|
||||
for (i = 0; i < txq->n_window; i++) {
|
||||
kzfree(txq->entries[i].cmd);
|
||||
kzfree(txq->entries[i].free_buf);
|
||||
|
@ -760,8 +758,9 @@ void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
|
|||
SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
|
||||
|
||||
/* make sure all queue are not stopped/used */
|
||||
memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
|
||||
memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
|
||||
memset(trans->txqs.queue_stopped, 0,
|
||||
sizeof(trans->txqs.queue_stopped));
|
||||
memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
|
||||
|
||||
trans_pcie->scd_base_addr =
|
||||
iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
|
||||
|
@ -783,9 +782,9 @@ void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
|
|||
if (trans->trans_cfg->base_params->scd_chain_ext_wa)
|
||||
iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
|
||||
|
||||
iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
|
||||
trans_pcie->cmd_fifo,
|
||||
trans_pcie->cmd_q_wdg_timeout);
|
||||
iwl_trans_ac_txq_enable(trans, trans->txqs.cmd.q_id,
|
||||
trans->txqs.cmd.fifo,
|
||||
trans->txqs.cmd.wdg_timeout);
|
||||
|
||||
/* Activate all Tx DMA/FIFO channels */
|
||||
iwl_scd_activate_fifos(trans);
|
||||
|
@ -821,7 +820,7 @@ void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
|
|||
|
||||
for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
|
||||
txq_id++) {
|
||||
struct iwl_txq *txq = trans_pcie->txq[txq_id];
|
||||
struct iwl_txq *txq = trans->txqs.txq[txq_id];
|
||||
if (trans->trans_cfg->use_tfh)
|
||||
iwl_write_direct64(trans,
|
||||
FH_MEM_CBBC_QUEUE(trans, txq_id),
|
||||
|
@ -897,8 +896,9 @@ int iwl_pcie_tx_stop(struct iwl_trans *trans)
|
|||
* queues. This happens when we have an rfkill interrupt.
|
||||
* Since we stop Tx altogether - mark the queues as stopped.
|
||||
*/
|
||||
memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
|
||||
memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
|
||||
memset(trans->txqs.queue_stopped, 0,
|
||||
sizeof(trans->txqs.queue_stopped));
|
||||
memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
|
||||
|
||||
/* This can happen: start_hw, stop_device */
|
||||
if (!trans_pcie->txq_memory)
|
||||
|
@ -922,7 +922,7 @@ void iwl_pcie_tx_free(struct iwl_trans *trans)
|
|||
int txq_id;
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
|
||||
memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
|
||||
memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
|
||||
|
||||
/* Tx queues */
|
||||
if (trans_pcie->txq_memory) {
|
||||
|
@ -930,7 +930,7 @@ void iwl_pcie_tx_free(struct iwl_trans *trans)
|
|||
txq_id < trans->trans_cfg->base_params->num_of_queues;
|
||||
txq_id++) {
|
||||
iwl_pcie_txq_free(trans, txq_id);
|
||||
trans_pcie->txq[txq_id] = NULL;
|
||||
trans->txqs.txq[txq_id] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -991,7 +991,7 @@ static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
|
|||
/* Alloc and init all Tx queues, including the command queue (#4/#9) */
|
||||
for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
|
||||
txq_id++) {
|
||||
bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
|
||||
bool cmd_queue = (txq_id == trans->txqs.cmd.q_id);
|
||||
|
||||
if (cmd_queue)
|
||||
slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
|
||||
|
@ -999,14 +999,14 @@ static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
|
|||
else
|
||||
slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
|
||||
trans->cfg->min_256_ba_txq_size);
|
||||
trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id];
|
||||
ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id],
|
||||
trans->txqs.txq[txq_id] = &trans_pcie->txq_memory[txq_id];
|
||||
ret = iwl_pcie_txq_alloc(trans, trans->txqs.txq[txq_id],
|
||||
slots_num, cmd_queue);
|
||||
if (ret) {
|
||||
IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
|
||||
goto error;
|
||||
}
|
||||
trans_pcie->txq[txq_id]->id = txq_id;
|
||||
trans->txqs.txq[txq_id]->id = txq_id;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
@ -1045,7 +1045,7 @@ int iwl_pcie_tx_init(struct iwl_trans *trans)
|
|||
/* Alloc and init all Tx queues, including the command queue (#4/#9) */
|
||||
for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
|
||||
txq_id++) {
|
||||
bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
|
||||
bool cmd_queue = (txq_id == trans->txqs.cmd.q_id);
|
||||
|
||||
if (cmd_queue)
|
||||
slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
|
||||
|
@ -1053,7 +1053,7 @@ int iwl_pcie_tx_init(struct iwl_trans *trans)
|
|||
else
|
||||
slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
|
||||
trans->cfg->min_256_ba_txq_size);
|
||||
ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id],
|
||||
ret = iwl_pcie_txq_init(trans, trans->txqs.txq[txq_id],
|
||||
slots_num, cmd_queue);
|
||||
if (ret) {
|
||||
IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
|
||||
|
@ -1067,7 +1067,7 @@ int iwl_pcie_tx_init(struct iwl_trans *trans)
|
|||
* Circular buffer (TFD queue in DRAM) physical base address
|
||||
*/
|
||||
iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
|
||||
trans_pcie->txq[txq_id]->dma_addr >> 8);
|
||||
trans->txqs.txq[txq_id]->dma_addr >> 8);
|
||||
}
|
||||
|
||||
iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
|
||||
|
@ -1112,18 +1112,18 @@ void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
|
|||
struct sk_buff_head *skbs)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *txq = trans_pcie->txq[txq_id];
|
||||
struct iwl_txq *txq = trans->txqs.txq[txq_id];
|
||||
int tfd_num = iwl_pcie_get_cmd_index(txq, ssn);
|
||||
int read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
|
||||
int last_to_free;
|
||||
|
||||
/* This function is not meant to release cmd queue*/
|
||||
if (WARN_ON(txq_id == trans_pcie->cmd_queue))
|
||||
if (WARN_ON(txq_id == trans->txqs.cmd.q_id))
|
||||
return;
|
||||
|
||||
spin_lock_bh(&txq->lock);
|
||||
|
||||
if (!test_bit(txq_id, trans_pcie->queue_used)) {
|
||||
if (!test_bit(txq_id, trans->txqs.queue_used)) {
|
||||
IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
|
||||
txq_id, ssn);
|
||||
goto out;
|
||||
|
@ -1175,7 +1175,7 @@ void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
|
|||
iwl_pcie_txq_progress(txq);
|
||||
|
||||
if (iwl_queue_space(trans, txq) > txq->low_mark &&
|
||||
test_bit(txq_id, trans_pcie->queue_stopped)) {
|
||||
test_bit(txq_id, trans->txqs.queue_stopped)) {
|
||||
struct sk_buff_head overflow_skbs;
|
||||
|
||||
__skb_queue_head_init(&overflow_skbs);
|
||||
|
@ -1228,8 +1228,7 @@ out:
|
|||
/* Set wr_ptr of specific device and txq */
|
||||
void iwl_trans_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *txq = trans_pcie->txq[txq_id];
|
||||
struct iwl_txq *txq = trans->txqs.txq[txq_id];
|
||||
|
||||
spin_lock_bh(&txq->lock);
|
||||
|
||||
|
@ -1289,7 +1288,7 @@ static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
|
|||
static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *txq = trans_pcie->txq[txq_id];
|
||||
struct iwl_txq *txq = trans->txqs.txq[txq_id];
|
||||
unsigned long flags;
|
||||
int nfreed = 0;
|
||||
u16 r;
|
||||
|
@ -1301,7 +1300,7 @@ static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
|
|||
|
||||
if (idx >= trans->trans_cfg->base_params->max_tfd_queue_size ||
|
||||
(!iwl_queue_used(txq, idx))) {
|
||||
WARN_ONCE(test_bit(txq_id, trans_pcie->queue_used),
|
||||
WARN_ONCE(test_bit(txq_id, trans->txqs.queue_used),
|
||||
"%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
|
||||
__func__, txq_id, idx,
|
||||
trans->trans_cfg->base_params->max_tfd_queue_size,
|
||||
|
@ -1363,11 +1362,11 @@ bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
|
|||
unsigned int wdg_timeout)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *txq = trans_pcie->txq[txq_id];
|
||||
struct iwl_txq *txq = trans->txqs.txq[txq_id];
|
||||
int fifo = -1;
|
||||
bool scd_bug = false;
|
||||
|
||||
if (test_and_set_bit(txq_id, trans_pcie->queue_used))
|
||||
if (test_and_set_bit(txq_id, trans->txqs.queue_used))
|
||||
WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
|
||||
|
||||
txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
|
||||
|
@ -1376,7 +1375,7 @@ bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
|
|||
fifo = cfg->fifo;
|
||||
|
||||
/* Disable the scheduler prior configuring the cmd queue */
|
||||
if (txq_id == trans_pcie->cmd_queue &&
|
||||
if (txq_id == trans->txqs.cmd.q_id &&
|
||||
trans_pcie->scd_set_active)
|
||||
iwl_scd_enable_set_active(trans, 0);
|
||||
|
||||
|
@ -1384,7 +1383,7 @@ bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
|
|||
iwl_scd_txq_set_inactive(trans, txq_id);
|
||||
|
||||
/* Set this queue as a chain-building queue unless it is CMD */
|
||||
if (txq_id != trans_pcie->cmd_queue)
|
||||
if (txq_id != trans->txqs.cmd.q_id)
|
||||
iwl_scd_txq_set_chain(trans, txq_id);
|
||||
|
||||
if (cfg->aggregate) {
|
||||
|
@ -1454,7 +1453,7 @@ bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
|
|||
SCD_QUEUE_STTS_REG_MSK);
|
||||
|
||||
/* enable the scheduler for this queue (only) */
|
||||
if (txq_id == trans_pcie->cmd_queue &&
|
||||
if (txq_id == trans->txqs.cmd.q_id &&
|
||||
trans_pcie->scd_set_active)
|
||||
iwl_scd_enable_set_active(trans, BIT(txq_id));
|
||||
|
||||
|
@ -1473,8 +1472,7 @@ bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
|
|||
void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
|
||||
bool shared_mode)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *txq = trans_pcie->txq[txq_id];
|
||||
struct iwl_txq *txq = trans->txqs.txq[txq_id];
|
||||
|
||||
txq->ampdu = !shared_mode;
|
||||
}
|
||||
|
@ -1487,8 +1485,8 @@ void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
|
|||
SCD_TX_STTS_QUEUE_OFFSET(txq_id);
|
||||
static const u32 zero_val[4] = {};
|
||||
|
||||
trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0;
|
||||
trans_pcie->txq[txq_id]->frozen = false;
|
||||
trans->txqs.txq[txq_id]->frozen_expiry_remainder = 0;
|
||||
trans->txqs.txq[txq_id]->frozen = false;
|
||||
|
||||
/*
|
||||
* Upon HW Rfkill - we stop the device, and then stop the queues
|
||||
|
@ -1496,7 +1494,7 @@ void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
|
|||
* allow the op_mode to call txq_disable after it already called
|
||||
* stop_device.
|
||||
*/
|
||||
if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
|
||||
if (!test_and_clear_bit(txq_id, trans->txqs.queue_used)) {
|
||||
WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
|
||||
"queue %d not used", txq_id);
|
||||
return;
|
||||
|
@ -1510,7 +1508,7 @@ void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
|
|||
}
|
||||
|
||||
iwl_pcie_txq_unmap(trans, txq_id);
|
||||
trans_pcie->txq[txq_id]->ampdu = false;
|
||||
trans->txqs.txq[txq_id]->ampdu = false;
|
||||
|
||||
IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
|
||||
}
|
||||
|
@ -1530,7 +1528,7 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
|
|||
struct iwl_host_cmd *cmd)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
|
||||
struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id];
|
||||
struct iwl_device_cmd *out_cmd;
|
||||
struct iwl_cmd_meta *out_meta;
|
||||
unsigned long flags;
|
||||
|
@ -1656,7 +1654,7 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
|
|||
sizeof(struct iwl_cmd_header_wide));
|
||||
out_cmd->hdr_wide.reserved = 0;
|
||||
out_cmd->hdr_wide.sequence =
|
||||
cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
|
||||
cpu_to_le16(QUEUE_TO_SEQ(trans->txqs.cmd.q_id) |
|
||||
INDEX_TO_SEQ(txq->write_ptr));
|
||||
|
||||
cmd_pos = sizeof(struct iwl_cmd_header_wide);
|
||||
|
@ -1664,7 +1662,7 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
|
|||
} else {
|
||||
out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
|
||||
out_cmd->hdr.sequence =
|
||||
cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
|
||||
cpu_to_le16(QUEUE_TO_SEQ(trans->txqs.cmd.q_id) |
|
||||
INDEX_TO_SEQ(txq->write_ptr));
|
||||
out_cmd->hdr.group_id = 0;
|
||||
|
||||
|
@ -1715,7 +1713,7 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
|
|||
iwl_get_cmd_string(trans, cmd->id),
|
||||
group_id, out_cmd->hdr.cmd,
|
||||
le16_to_cpu(out_cmd->hdr.sequence),
|
||||
cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
|
||||
cmd_size, txq->write_ptr, idx, trans->txqs.cmd.q_id);
|
||||
|
||||
/* start the TFD with the minimum copy bytes */
|
||||
tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
|
||||
|
@ -1815,14 +1813,14 @@ void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
|
|||
struct iwl_device_cmd *cmd;
|
||||
struct iwl_cmd_meta *meta;
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
|
||||
struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id];
|
||||
|
||||
/* If a Tx command is being handled and it isn't in the actual
|
||||
* command queue then there a command routing bug has been introduced
|
||||
* in the queue management code. */
|
||||
if (WARN(txq_id != trans_pcie->cmd_queue,
|
||||
if (WARN(txq_id != trans->txqs.cmd.q_id,
|
||||
"wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
|
||||
txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr,
|
||||
txq_id, trans->txqs.cmd.q_id, sequence, txq->read_ptr,
|
||||
txq->write_ptr)) {
|
||||
iwl_print_hex_error(trans, pkt, 32);
|
||||
return;
|
||||
|
@ -1894,7 +1892,7 @@ static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
|
|||
struct iwl_host_cmd *cmd)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
|
||||
struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id];
|
||||
int cmd_idx;
|
||||
int ret;
|
||||
|
||||
|
@ -2332,9 +2330,9 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
|
|||
u16 wifi_seq;
|
||||
bool amsdu;
|
||||
|
||||
txq = trans_pcie->txq[txq_id];
|
||||
txq = trans->txqs.txq[txq_id];
|
||||
|
||||
if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
|
||||
if (WARN_ONCE(!test_bit(txq_id, trans->txqs.queue_used),
|
||||
"TX on unused queue %d\n", txq_id))
|
||||
return -EINVAL;
|
||||
|
||||
|
|
Loading…
Reference in New Issue