[PATCH] ARM SMP: Fix ARMv6 spinlock and semaphore implementations
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -61,7 +61,7 @@
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" strex ip, lr, [%0]\n" \
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" teq ip, #0\n" \
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" bne 1b\n" \
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" teq lr, #0\n" \
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" cmp lr, #0\n" \
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" movle ip, %0\n" \
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" blle " #wake \
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: \
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@ -100,7 +100,7 @@
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__asm__ __volatile__( \
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"@ up_op_read\n" \
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"1: ldrex lr, [%0]\n" \
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" add lr, lr, %1\n" \
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" adds lr, lr, %1\n" \
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" strex ip, lr, [%0]\n" \
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" teq ip, #0\n" \
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" bne 1b\n" \
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@ -79,7 +79,8 @@ typedef struct {
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} rwlock_t;
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#define RW_LOCK_UNLOCKED (rwlock_t) { 0 }
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#define rwlock_init(x) do { *(x) + RW_LOCK_UNLOCKED; } while (0)
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#define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while (0)
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#define rwlock_is_locked(x) (*((volatile unsigned int *)(x)) != 0)
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/*
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* Write locks are easy - we just set bit 31. When unlocking, we can
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@ -100,6 +101,21 @@ static inline void _raw_write_lock(rwlock_t *rw)
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: "cc", "memory");
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}
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static inline int _raw_write_trylock(rwlock_t *rw)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldrex %0, [%1]\n"
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" teq %0, #0\n"
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" strexeq %0, %2, [%1]"
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: "=&r" (tmp)
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: "r" (&rw->lock), "r" (0x80000000)
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: "cc", "memory");
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return tmp == 0;
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}
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static inline void _raw_write_unlock(rwlock_t *rw)
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{
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__asm__ __volatile__(
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@ -138,6 +154,8 @@ static inline void _raw_read_lock(rwlock_t *rw)
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static inline void _raw_read_unlock(rwlock_t *rw)
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{
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unsigned long tmp, tmp2;
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__asm__ __volatile__(
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"1: ldrex %0, [%2]\n"
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" sub %0, %0, #1\n"
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@ -151,19 +169,4 @@ static inline void _raw_read_unlock(rwlock_t *rw)
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#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
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static inline int _raw_write_trylock(rwlock_t *rw)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldrex %0, [%1]\n"
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" teq %0, #0\n"
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" strexeq %0, %2, [%1]"
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: "=&r" (tmp)
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: "r" (&rw->lock), "r" (0x80000000)
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: "cc", "memory");
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return tmp == 0;
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}
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#endif /* __ASM_SPINLOCK_H */
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