vfio/pci: Use kernel VPD access functions
The PCI VPD capability operates on a set of window registers in PCI config space. Writing to the address register triggers either a read or write, depending on the setting of the PCI_VPD_ADDR_F bit within the address register. The data register provides either the source for writes or the target for reads. This model is susceptible to being broken by concurrent access, for which the kernel has adopted a set of access functions to serialize these registers. Additionally, commits like932c435cab
("PCI: Add dev_flags bit to access VPD through function 0") and7aa6ca4d39
("PCI: Add VPD function 0 quirk for Intel Ethernet devices") indicate that VPD registers can be shared between functions on multifunction devices creating dependencies between otherwise independent devices. Fortunately it's quite easy to emulate the VPD registers, simply storing copies of the address and data registers in memory and triggering a VPD read or write on writes to the address register. This allows vfio users to avoid seeing spurious register changes from accesses on other devices and enables the use of shared quirks in the host kernel. We can theoretically still race with access through sysfs, but the window of opportunity is much smaller. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Acked-by: Mark Rustad <mark.d.rustad@intel.com>
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@ -671,6 +671,73 @@ static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
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return 0;
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}
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static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos,
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int count, struct perm_bits *perm,
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int offset, __le32 val)
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{
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struct pci_dev *pdev = vdev->pdev;
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__le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR);
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__le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA);
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u16 addr;
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u32 data;
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/*
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* Write through to emulation. If the write includes the upper byte
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* of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we
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* have work to do.
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*/
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count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
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if (count < 0 || offset > PCI_VPD_ADDR + 1 ||
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offset + count <= PCI_VPD_ADDR + 1)
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return count;
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addr = le16_to_cpu(*paddr);
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if (addr & PCI_VPD_ADDR_F) {
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data = le32_to_cpu(*pdata);
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if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4)
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return count;
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} else {
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if (pci_read_vpd(pdev, addr, 4, &data) != 4)
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return count;
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*pdata = cpu_to_le32(data);
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}
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/*
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* Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to
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* signal completion. If an error occurs above, we assume that not
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* toggling this bit will induce a driver timeout.
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*/
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addr ^= PCI_VPD_ADDR_F;
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*paddr = cpu_to_le16(addr);
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return count;
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}
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/* Permissions for Vital Product Data capability */
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static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
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{
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if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
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return -ENOMEM;
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perm->writefn = vfio_vpd_config_write;
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/*
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* We always virtualize the next field so we can remove
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* capabilities from the chain if we want to.
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*/
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p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
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/*
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* Both the address and data registers are virtualized to
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* enable access through the pci_vpd_read/write functions
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*/
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p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
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p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
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return 0;
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}
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/* Permissions for PCI-X capability */
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static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
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{
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@ -790,6 +857,7 @@ void vfio_pci_uninit_perm_bits(void)
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free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]);
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free_perm_bits(&cap_perms[PCI_CAP_ID_PM]);
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free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]);
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free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]);
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free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]);
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free_perm_bits(&cap_perms[PCI_CAP_ID_AF]);
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@ -807,7 +875,7 @@ int __init vfio_pci_init_perm_bits(void)
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/* Capabilities */
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ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]);
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cap_perms[PCI_CAP_ID_VPD].writefn = vfio_raw_config_write;
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ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]);
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ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]);
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cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write;
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ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]);
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