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mmc: sdhci-cadence: fix bit shift of read data from PHY port 

This macro is currently unused, but it may be useful for debug use.
Fix it just in case.

Fixes: ff6af28faf ("mmc: sdhci-cadence: add Cadence SD4HC support")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Masahiro Yamada 2017-02-14 20:05:40 +09:00 committed by Ulf Hansson
parent 006cac8262
commit 4e03f628b4
1 changed files with 1 additions and 1 deletions
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2
drivers/mmc/host/sdhci-cadence.c
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@ -26,7 +26,7 @@
#define SDHCI_CDNS_HRS04_ACK BIT(26)
#define SDHCI_CDNS_HRS04_RD BIT(25)
#define SDHCI_CDNS_HRS04_WR BIT(24)
#define SDHCI_CDNS_HRS04_RDATA_SHIFT 12
#define SDHCI_CDNS_HRS04_RDATA_SHIFT 16
#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8
#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0