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cxgb4: collect HMA memory dump 

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Rahul Lakkireddy 2017-12-08 09:48:38 +05:30 committed by David S. Miller
parent a1c69520f7
commit 4db0401f8a
9 changed files with 51 additions and 4 deletions
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1
drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
View File

@ -23,6 +23,7 @@
#define MC_FLAG 2
#define MC0_FLAG 3
#define MC1_FLAG 4
#define HMA_FLAG 5
#define CUDBG_ENTITY_SIGNATURE 0xCCEDB001

1
drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
View File

@ -77,6 +77,7 @@ enum cudbg_dbg_entity_type {
CUDBG_PBT_TABLE = 65,
CUDBG_MBOX_LOG = 66,
CUDBG_HMA_INDIRECT = 67,
CUDBG_HMA = 68,
CUDBG_MAX_ENTITY = 70,
};

22
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
View File

@ -169,6 +169,17 @@ int cudbg_fill_meminfo(struct adapter *padap,
meminfo_buff->avail[i].idx = 2;
i++;
}
if (lo & HMA_MUX_F) {
hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
meminfo_buff->avail[i].base =
cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
meminfo_buff->avail[i].limit =
meminfo_buff->avail[i].base +
cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
meminfo_buff->avail[i].idx = 5;
i++;
}
}
if (!i) /* no memory available */
@ -702,6 +713,9 @@ static int cudbg_meminfo_get_mem_index(struct adapter *padap,
case MEM_MC1:
flag = MC1_FLAG;
break;
case MEM_HMA:
flag = HMA_FLAG;
break;
default:
return CUDBG_STATUS_ENTITY_NOT_FOUND;
}
@ -835,6 +849,14 @@ int cudbg_collect_mc1_meminfo(struct cudbg_init *pdbg_init,
MEM_MC1);
}
int cudbg_collect_hma_meminfo(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
{
return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
MEM_HMA);
}
int cudbg_collect_rss(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)

3
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h
View File

@ -165,6 +165,9 @@ int cudbg_collect_mbox_log(struct cudbg_init *pdbg_init,
int cudbg_collect_hma_indirect(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);
int cudbg_collect_hma_meminfo(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);
struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i);
void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff,

3
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
View File

@ -77,7 +77,8 @@ enum {
MEM_EDC1,
MEM_MC,
MEM_MC0 = MEM_MC,
MEM_MC1
MEM_MC1,
MEM_HMA,
};
enum {

12
drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
View File

@ -24,6 +24,7 @@ static const struct cxgb4_collect_entity cxgb4_collect_mem_dump[] = {
{ CUDBG_EDC1, cudbg_collect_edc1_meminfo },
{ CUDBG_MC0, cudbg_collect_mc0_meminfo },
{ CUDBG_MC1, cudbg_collect_mc1_meminfo },
{ CUDBG_HMA, cudbg_collect_hma_meminfo },
};
static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
@ -285,6 +286,17 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
len = sizeof(struct ireg_buf) * n;
}
break;
case CUDBG_HMA:
value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
if (value & HMA_MUX_F) {
/* In T6, there's no MC1. So, HMA shares MC1
* address space.
*/
value = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
len = EXT_MEM1_SIZE_G(value);
}
len = cudbg_mbytes_to_bytes(len);
break;
default:
break;
}

2
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
View File

@ -2811,7 +2811,7 @@ static void mem_region_show(struct seq_file *seq, const char *name,
static int meminfo_show(struct seq_file *seq, void *v)
{
static const char * const memory[] = { "EDC0:", "EDC1:", "MC:",
"MC0:", "MC1:"};
"MC0:", "MC1:", "HMA:"};
struct adapter *adap = seq->private;
struct cudbg_meminfo meminfo;
int i, rc;

7
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
View File

@ -524,11 +524,14 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
* MEM_EDC1 = 1
* MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
* MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
* MEM_HMA = 4
*/
edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
if (mtype != MEM_MC1)
if (mtype == MEM_HMA) {
memoffset = 2 * (edc_size * 1024 * 1024);
} else if (mtype != MEM_MC1) {
memoffset = (mtype * (edc_size * 1024 * 1024));
else {
} else {
mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
MA_EXT_MEMORY0_BAR_A));
memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;

4
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
View File

@ -961,6 +961,10 @@
#define MA_EXT_MEMORY1_BAR_A 0x7808
#define HMA_MUX_S 5
#define HMA_MUX_V(x) ((x) << HMA_MUX_S)
#define HMA_MUX_F HMA_MUX_V(1U)
#define EXT_MEM1_BASE_S 16
#define EXT_MEM1_BASE_M 0xfffU
#define EXT_MEM1_BASE_G(x) (((x) >> EXT_MEM1_BASE_S) & EXT_MEM1_BASE_M)