drm/amd/powerplay: refine code to avoid potential bug that the memory not cleared.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -4398,16 +4398,14 @@ static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
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if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL)
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return -EINVAL;
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dep_sclk_table = table_info->vdd_dep_on_sclk;
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for (i = 0; i < dep_sclk_table->count; i++) {
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for (i = 0; i < dep_sclk_table->count; i++)
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clocks->clock[i] = dep_sclk_table->entries[i].clk;
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clocks->count++;
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}
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clocks->count = dep_sclk_table->count;
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} else if (hwmgr->pp_table_version == PP_TABLE_V0) {
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sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
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for (i = 0; i < sclk_table->count; i++) {
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for (i = 0; i < sclk_table->count; i++)
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clocks->clock[i] = sclk_table->entries[i].clk;
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clocks->count++;
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}
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clocks->count = sclk_table->count;
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}
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return 0;
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@ -4441,14 +4439,13 @@ static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
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clocks->clock[i] = dep_mclk_table->entries[i].clk;
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clocks->latency[i] = smu7_get_mem_latency(hwmgr,
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dep_mclk_table->entries[i].clk);
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clocks->count++;
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}
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clocks->count = dep_mclk_table->count;
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} else if (hwmgr->pp_table_version == PP_TABLE_V0) {
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mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
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for (i = 0; i < mclk_table->count; i++) {
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for (i = 0; i < mclk_table->count; i++)
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clocks->clock[i] = mclk_table->entries[i].clk;
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clocks->count++;
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}
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clocks->count = mclk_table->count;
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}
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return 0;
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}
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