ASoC: rockchip: i2s: add 8 channels capture support
support max 8 channels capture, please add property 'rockchip,capture-channels' in dts to enable this, if not, support 2 channels capture default. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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13531520e3
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4c9c018b2a
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@ -245,8 +245,34 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, I2S_TXCR, I2S_TXCR_VDW_MASK, val);
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regmap_update_bits(i2s->regmap, I2S_RXCR, I2S_RXCR_VDW_MASK, val);
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switch (params_channels(params)) {
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case 8:
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val |= I2S_CHN_8;
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break;
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case 6:
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val |= I2S_CHN_6;
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break;
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case 4:
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val |= I2S_CHN_4;
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break;
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case 2:
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val |= I2S_CHN_2;
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break;
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default:
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dev_err(i2s->dev, "invalid channel: %d\n",
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params_channels(params));
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return -EINVAL;
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}
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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regmap_update_bits(i2s->regmap, I2S_RXCR,
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I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
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val);
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else
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regmap_update_bits(i2s->regmap, I2S_TXCR,
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I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
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val);
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regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
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I2S_DMACR_TDL(16));
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regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
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@ -415,10 +441,12 @@ static const struct regmap_config rockchip_i2s_regmap_config = {
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static int rockchip_i2s_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct rk_i2s_dev *i2s;
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struct resource *res;
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void __iomem *regs;
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int ret;
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int val;
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i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
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if (!i2s) {
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@ -475,6 +503,14 @@ static int rockchip_i2s_probe(struct platform_device *pdev)
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goto err_pm_disable;
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}
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/* refine capture channels */
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if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
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if (val >= 2 && val <= 8)
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rockchip_i2s_dai.capture.channels_max = val;
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else
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rockchip_i2s_dai.capture.channels_max = 2;
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}
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ret = devm_snd_soc_register_component(&pdev->dev,
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&rockchip_i2s_component,
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&rockchip_i2s_dai, 1);
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@ -49,6 +49,9 @@
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* RXCR
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* receive operation control register
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*/
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#define I2S_RXCR_CSR_SHIFT 15
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#define I2S_RXCR_CSR(x) (x << I2S_RXCR_CSR_SHIFT)
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#define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT)
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#define I2S_RXCR_HWT BIT(14)
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#define I2S_RXCR_SJM_SHIFT 12
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#define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT)
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@ -207,6 +210,13 @@ enum {
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ROCKCHIP_DIV_BCLK,
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};
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/* channel select */
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#define I2S_CSR_SHIFT 15
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#define I2S_CHN_2 (0 << I2S_CSR_SHIFT)
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#define I2S_CHN_4 (1 << I2S_CSR_SHIFT)
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#define I2S_CHN_6 (2 << I2S_CSR_SHIFT)
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#define I2S_CHN_8 (3 << I2S_CSR_SHIFT)
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/* I2S REGS */
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#define I2S_TXCR (0x0000)
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#define I2S_RXCR (0x0004)
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