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Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull timer fixes from Thomas Gleixner:
 "A small set of fixes from the timer departement:

   - Add a missing timer wheel clock forward when migrating timers off a
     unplugged CPU to prevent operating on a stale clock base and
     missing timer deadlines.

   - Use the proper shift count to extract data from a register value to
     prevent evaluating unrelated bits

   - Make the error return check in the FSL timer driver work correctly.
     Checking an unsigned variable for less than zero does not really
     work well.

   - Clarify the confusing comments in the ARC timer code"

* 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  timers: Forward timer base before migrating timers
  clocksource/drivers/arc_timer: Update some comments
  clocksource/drivers/mips-gic-timer: Use correct shift count to extract data
  clocksource/drivers/fsl_ftm_timer: Fix error return checking
This commit is contained in:
Linus Torvalds 2018-03-04 11:34:49 -08:00
parent ff8d583621 c52232a49e
commit 4c4ce3022d
4 changed files with 16 additions and 5 deletions
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11
drivers/clocksource/arc_timer.c
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@ -251,9 +251,14 @@ static irqreturn_t timer_irq_handler(int irq, void *dev_id)
int irq_reenable = clockevent_state_periodic(evt); int irq_reenable = clockevent_state_periodic(evt);
/* /*
* Any write to CTRL reg ACks the interrupt, we rewrite the * 1. ACK the interrupt
* Count when [N]ot [H]alted bit. * - For ARC700, any write to CTRL reg ACKs it, so just rewrite
* And re-arm it if perioid by [I]nterrupt [E]nable bit * Count when [N]ot [H]alted bit.
* - For HS3x, it is a bit subtle. On taken count-down interrupt,
* IP bit [3] is set, which needs to be cleared for ACK'ing.
* The write below can only update the other two bits, hence
* explicitly clears IP bit
* 2. Re-arm interrupt if periodic by writing to IE bit [0]
*/ */
write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);

2
drivers/clocksource/fsl_ftm_timer.c
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@ -281,7 +281,7 @@ static int __init __ftm_clk_init(struct device_node *np, char *cnt_name,
static unsigned long __init ftm_clk_init(struct device_node *np) static unsigned long __init ftm_clk_init(struct device_node *np)
{ {
unsigned long freq; long freq;
freq = __ftm_clk_init(np, "ftm-evt-counter-en", "ftm-evt"); freq = __ftm_clk_init(np, "ftm-evt-counter-en", "ftm-evt");
if (freq <= 0) if (freq <= 0)

2
drivers/clocksource/mips-gic-timer.c
View File

@ -166,7 +166,7 @@ static int __init __gic_clocksource_init(void)
/* Set clocksource mask. */ /* Set clocksource mask. */
count_width = read_gic_config() & GIC_CONFIG_COUNTBITS; count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
count_width >>= __fls(GIC_CONFIG_COUNTBITS); count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
count_width *= 4; count_width *= 4;
count_width += 32; count_width += 32;
gic_clocksource.mask = CLOCKSOURCE_MASK(count_width); gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);

6
kernel/time/timer.c
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@ -1894,6 +1894,12 @@ int timers_dead_cpu(unsigned int cpu)
raw_spin_lock_irq(&new_base->lock); raw_spin_lock_irq(&new_base->lock);
raw_spin_lock_nested(&old_base->lock, SINGLE_DEPTH_NESTING); raw_spin_lock_nested(&old_base->lock, SINGLE_DEPTH_NESTING);
/*
* The current CPUs base clock might be stale. Update it
* before moving the timers over.
*/
forward_timer_base(new_base);
BUG_ON(old_base->running_timer); BUG_ON(old_base->running_timer);
for (i = 0; i < WHEEL_SIZE; i++) for (i = 0; i < WHEEL_SIZE; i++)