drm/i915: fix locking around ironlake_enable|disable_display_irq
The haswell unclaimed register handling code forgot to take the spinlock. Since this is in the context of the non-rentrant interupt handler and we only have one interrupt handler it is sufficient to just grab the spinlock - we do not need to exclude any other interrupts from running on the same cpu. To prevent such gaffles in the future sprinkle assert_spin_locked over these functions. Unfornately this requires us to hold the spinlock in the ironlake postinstall hook where it is not strictly required: Currently that is run in single-threaded context and with userspace exlcuded from running concurrent ioctls. Add a comment explaining this. v2: ivb_can_enable_err_int also needs to be protected by the spinlock. To ensure this won't happen in the future again also sprinkle a spinlock assert in there. v3: Kill the 2nd call to ivb_can_enable_err_int I've accidentally left behind, spotted by Paulo. Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by: Paulo Zanoni <przanoni@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -86,6 +86,8 @@ static void i915_hpd_irq_setup(struct drm_device *dev);
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static void
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ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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assert_spin_locked(&dev_priv->irq_lock);
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if ((dev_priv->irq_mask & mask) != 0) {
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dev_priv->irq_mask &= ~mask;
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I915_WRITE(DEIMR, dev_priv->irq_mask);
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@ -96,6 +98,8 @@ ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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static void
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ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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assert_spin_locked(&dev_priv->irq_lock);
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if ((dev_priv->irq_mask & mask) != mask) {
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dev_priv->irq_mask |= mask;
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I915_WRITE(DEIMR, dev_priv->irq_mask);
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@ -109,6 +113,8 @@ static bool ivb_can_enable_err_int(struct drm_device *dev)
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struct intel_crtc *crtc;
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enum pipe pipe;
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assert_spin_locked(&dev_priv->irq_lock);
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for_each_pipe(pipe) {
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crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
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@ -1217,8 +1223,11 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
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/* On Haswell, also mask ERR_INT because we don't want to risk
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* generating "unclaimed register" interrupts from inside the interrupt
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* handler. */
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if (IS_HASWELL(dev))
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if (IS_HASWELL(dev)) {
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spin_lock(&dev_priv->irq_lock);
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ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
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spin_unlock(&dev_priv->irq_lock);
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}
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gt_iir = I915_READ(GTIIR);
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if (gt_iir) {
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@ -1271,8 +1280,12 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
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ret = IRQ_HANDLED;
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}
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if (IS_HASWELL(dev) && ivb_can_enable_err_int(dev))
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ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
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if (IS_HASWELL(dev)) {
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spin_lock(&dev_priv->irq_lock);
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if (ivb_can_enable_err_int(dev))
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ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
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spin_unlock(&dev_priv->irq_lock);
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}
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I915_WRITE(DEIER, de_ier);
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POSTING_READ(DEIER);
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@ -2697,6 +2710,8 @@ static void ibx_irq_postinstall(struct drm_device *dev)
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static int ironlake_irq_postinstall(struct drm_device *dev)
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{
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unsigned long irqflags;
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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/* enable kind of interrupts always enabled */
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u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
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@ -2735,7 +2750,13 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
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/* Clear & enable PCU event interrupts */
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I915_WRITE(DEIIR, DE_PCU_EVENT);
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I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
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/* spinlocking not required here for correctness since interrupt
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* setup is guaranteed to run in single-threaded context. But we
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* need it to make the assert_spin_locked happy. */
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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}
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return 0;
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