arm: Xilinx(Zynq and ZynqMP) DT changes for v4.17
- Use SPDX license identifier - Add Xilinx ZynqMP boards zcu100-revC, zcu102-revA/revB/rev1.0, zcu104-revA, zcu106-revA, zcu111-revA, zc1751 dc1/dc2/dc3/dc4 - Add Xilinx Zynq boards cc108, zc770 dc1/dc2/dc3/dc4 - Add Digilent Zybo Z7 - Minor fixes in current DTSes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlqg4+cACgkQykllyylKDCFqOACfbtI4S2j96N3AsHy3sWFUP7li XlUAn2bSg/d/x8gSSt5bO2SlGqWkOQxw =iZic -----END PGP SIGNATURE----- Merge tag 'xilinx-dt-for-4.17' of https://github.com/Xilinx/linux-xlnx into next/dt Pull "arm: Xilinx(Zynq and ZynqMP) DT changes for v4.17" from Michal Simek: - Use SPDX license identifier - Add Xilinx ZynqMP boards zcu100-revC, zcu102-revA/revB/rev1.0, zcu104-revA, zcu106-revA, zcu111-revA, zc1751 dc1/dc2/dc3/dc4 - Add Xilinx Zynq boards cc108, zc770 dc1/dc2/dc3/dc4 - Add Digilent Zybo Z7 - Minor fixes in current DTSes * tag 'xilinx-dt-for-4.17' of https://github.com/Xilinx/linux-xlnx: (22 commits) arm: dts: zynq: Add Digilent Zybo Z7 board arm: zynq: Add support for Xilinx zc770 xm013 dc4 board arm: zynq: Add support for Xilinx zc770 xm012 dc3 board arm: zynq: Add support for Xilinx zc770 xm011 dc2 board arm: zynq: Add support for Xilinx zc770 xm010 dc1 board arm: zynq: Add Xilinx cc108 board arm: zynq: Add missing address node name in microzed board arm: dts: zynq: Use SPDX-License-Identifier arm: zynq: Use i2c-mux instead of i2cswitch for pca9548 arm64: zynqmp: Add support for Xilinx zc1751 arm64: zynqmp: Add support for Xilinx zc12XX boards arm64: zynqmp: Add support for Xilinx zcu111-revA arm64: zynqmp: Add support for Xilinx zcu106-revA arm64: zynqmp: Add support for Xilinx zcu104-revA arm64: zynqmp: Add support for Xilinx zcu102 arm64: zynqmp: Add support for Xilinx zcu100-revC dt-bindings: xilinx: Add description for ZynqMP arm64: zynqmp: Add 8-bit bus width property for ep108 arm64: zynqmp: Added OOB timing settings in zynqmp-ep108.dts arm64: zynqmp: Add SPDX license identifier ...
This commit is contained in:
Arnd Bergmann
commit
4bb4aceae9
|
|
@ -5,3 +5,59 @@ shall have the following properties.
|
|||
|
||||
Required root node properties:
|
||||
- compatible = "xlnx,zynq-7000";
|
||||
|
||||
Additional compatible strings:
|
||||
|
||||
- Xilinx internal board cc108
|
||||
"xlnx,zynq-cc108"
|
||||
|
||||
- Xilinx internal board zc770 with different FMC cards
|
||||
"xlnx,zynq-zc770-xm010"
|
||||
"xlnx,zynq-zc770-xm011"
|
||||
"xlnx,zynq-zc770-xm012"
|
||||
"xlnx,zynq-zc770-xm013"
|
||||
|
||||
- Digilent Zybo Z7 board
|
||||
"digilent,zynq-zybo-z7"
|
||||
|
||||
---------------------------------------------------------------
|
||||
|
||||
Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings
|
||||
|
||||
Boards with ZynqMP SOC based on an ARM Cortex A53 processor
|
||||
shall have the following properties.
|
||||
|
||||
Required root node properties:
|
||||
- compatible = "xlnx,zynqmp";
|
||||
|
||||
|
||||
Additional compatible strings:
|
||||
|
||||
- Xilinx internal board zc1232
|
||||
"xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232"
|
||||
|
||||
- Xilinx internal board zc1254
|
||||
"xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254"
|
||||
|
||||
- Xilinx internal board zc1275
|
||||
"xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275"
|
||||
|
||||
- Xilinx internal board zc1751
|
||||
"xlnx,zynqmp-zc1751"
|
||||
|
||||
- Xilinx 96boards compatible board zcu100
|
||||
"xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100"
|
||||
|
||||
- Xilinx evaluation board zcu102
|
||||
"xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102"
|
||||
"xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102"
|
||||
"xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102"
|
||||
|
||||
- Xilinx evaluation board zcu104
|
||||
"xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104"
|
||||
|
||||
- Xilinx evaluation board zcu106
|
||||
"xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106"
|
||||
|
||||
- Xilinx evaluation board zcu111
|
||||
"xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111"
|
||||
|
|
|
|||
|
|
@ -1070,12 +1070,18 @@ dtb-$(CONFIG_ARCH_VT8500) += \
|
|||
wm8750-apc8750.dtb \
|
||||
wm8850-w70v2.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQ) += \
|
||||
zynq-cc108.dtb \
|
||||
zynq-microzed.dtb \
|
||||
zynq-parallella.dtb \
|
||||
zynq-zc702.dtb \
|
||||
zynq-zc706.dtb \
|
||||
zynq-zc770-xm010.dtb \
|
||||
zynq-zc770-xm011.dtb \
|
||||
zynq-zc770-xm012.dtb \
|
||||
zynq-zc770-xm013.dtb \
|
||||
zynq-zed.dtb \
|
||||
zynq-zybo.dtb
|
||||
zynq-zybo.dtb \
|
||||
zynq-zybo-z7.dtb
|
||||
dtb-$(CONFIG_MACH_ARMADA_370) += \
|
||||
armada-370-db.dtb \
|
||||
armada-370-dlink-dns327l.dtb \
|
||||
|
|
|
|||
|
|
@ -1,14 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2011 - 2014 Xilinx
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
* Copyright (C) 2011 - 2014 Xilinx
|
||||
*/
|
||||
|
||||
/ {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,75 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Xilinx CC108 board DTS
|
||||
*
|
||||
* (C) Copyright 2007-2018 Xilinx, Inc.
|
||||
* (C) Copyright 2007-2013 Michal Simek
|
||||
* (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
|
||||
*
|
||||
* Michal SIMEK <monstr@monstr.eu>
|
||||
*/
|
||||
/dts-v1/;
|
||||
/include/ "zynq-7000.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000";
|
||||
model = "Xilinx Zynq";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem0;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x20000000>;
|
||||
};
|
||||
|
||||
usb_phy0: phy0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
usb_phy1: phy1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðernet_phy>;
|
||||
|
||||
ethernet_phy: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
broken-cd ;
|
||||
wp-inverted ;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
usb-phy = <&usb_phy0>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
usb-phy = <&usb_phy1>;
|
||||
};
|
||||
|
|
@ -1,15 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2011 - 2014 Xilinx
|
||||
* Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/include/ "zynq-7000.dtsi"
|
||||
|
|
@ -23,7 +15,7 @@
|
|||
serial0 = &uart1;
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2014 SUSE LINUX Products GmbH
|
||||
*
|
||||
|
|
@ -6,15 +7,6 @@
|
|||
* Copyright (C) 2011 Xilinx
|
||||
* Copyright (C) 2012 National Instruments Corp.
|
||||
* Copyright (C) 2013 Xilinx
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/include/ "zynq-7000.dtsi"
|
||||
|
|
|
|||
|
|
@ -1,15 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2011 - 2014 Xilinx
|
||||
* Copyright (C) 2012 National Instruments Corp.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "zynq-7000.dtsi"
|
||||
|
|
@ -112,7 +104,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
|
||||
i2cswitch@74 {
|
||||
i2c-mux@74 {
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -1,15 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2011 - 2014 Xilinx
|
||||
* Copyright (C) 2012 National Instruments Corp.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "zynq-7000.dtsi"
|
||||
|
|
@ -68,7 +60,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
|
||||
i2cswitch@74 {
|
||||
i2c-mux@74 {
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,95 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Xilinx ZC770 XM010 board DTS
|
||||
*
|
||||
* Copyright (C) 2013-2018 Xilinx, Inc.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "zynq-7000.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
|
||||
model = "Xilinx Zynq";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem0;
|
||||
i2c0 = &i2c0;
|
||||
serial0 = &uart1;
|
||||
spi1 = &spi1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>;
|
||||
};
|
||||
|
||||
usb_phy0: phy0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðernet_phy>;
|
||||
|
||||
ethernet_phy: ethernet-phy@7 {
|
||||
reg = <7>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
eeprom: eeprom@52 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x52>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
num-cs = <4>;
|
||||
is-decoded-cs = <0>;
|
||||
flash@0 {
|
||||
compatible = "sst25wf080", "jedec,spi-nor";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <1000000>;
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "data";
|
||||
reg = <0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
usb-phy = <&usb_phy0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Xilinx ZC770 XM013 board DTS
|
||||
*
|
||||
* Copyright (C) 2013-2018 Xilinx, Inc.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "zynq-7000.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
|
||||
model = "Xilinx Zynq";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c1;
|
||||
serial0 = &uart1;
|
||||
spi0 = &spi0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>;
|
||||
};
|
||||
|
||||
usb_phy1: phy1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
eeprom: eeprom@52 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x52>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
num-cs = <4>;
|
||||
is-decoded-cs = <0>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
usb-phy = <&usb_phy1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Xilinx ZC770 XM012 board DTS
|
||||
*
|
||||
* Copyright (C) 2013-2018 Xilinx, Inc.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "zynq-7000.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
|
||||
model = "Xilinx Zynq";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
serial0 = &uart1;
|
||||
spi0 = &spi1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
eeprom0: eeprom@52 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x52>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
eeprom1: eeprom@52 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x52>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
num-cs = <4>;
|
||||
is-decoded-cs = <0>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Xilinx ZC770 XM013 board DTS
|
||||
*
|
||||
* Copyright (C) 2013 Xilinx, Inc.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "zynq-7000.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
|
||||
model = "Xilinx Zynq";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem1;
|
||||
i2c0 = &i2c1;
|
||||
serial0 = &uart0;
|
||||
spi1 = &spi0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem1 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðernet_phy>;
|
||||
|
||||
ethernet_phy: ethernet-phy@7 {
|
||||
reg = <7>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
si570: clock-generator@55 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
temperature-stability = <50>;
|
||||
reg = <0x55>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
num-cs = <4>;
|
||||
is-decoded-cs = <0>;
|
||||
eeprom: eeprom@0 {
|
||||
at25,byte-len = <8192>;
|
||||
at25,addr-mode = <2>;
|
||||
at25,page-size = <32>;
|
||||
|
||||
compatible = "atmel,at25";
|
||||
reg = <2>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,15 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2011 - 2014 Xilinx
|
||||
* Copyright (C) 2012 National Instruments Corp.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "zynq-7000.dtsi"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,58 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/dts-v1/;
|
||||
#include "zynq-7000.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Zynq ZYBO Z7 Development Board";
|
||||
compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem0;
|
||||
serial0 = &uart1;
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x20000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
usb_phy0: phy0 {
|
||||
#phy-cells = <0>;
|
||||
compatible = "usb-nop-xceiv";
|
||||
reset-gpios = <&gpio0 46 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&clkc {
|
||||
ps-clk-frequency = <33333333>;
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðernet_phy>;
|
||||
|
||||
ethernet_phy: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
usb-phy = <&usb_phy0>;
|
||||
};
|
||||
|
|
@ -1,15 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2011 - 2014 Xilinx
|
||||
* Copyright (C) 2012 National Instruments Corp.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "zynq-7000.dtsi"
|
||||
|
|
|
|||
|
|
@ -1 +1,17 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm018-dc4.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm019-dc5.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb
|
||||
|
|
|
|||
|
|
@ -0,0 +1,213 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Clock specification for Xilinx ZynqMP
|
||||
*
|
||||
* (C) Copyright 2015 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/ {
|
||||
clk100: clk100 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
clk125: clk125 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
clk200: clk200 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
clk250: clk250 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
|
||||
clk300: clk300 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <300000000>;
|
||||
};
|
||||
|
||||
clk600: clk600 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <600000000>;
|
||||
};
|
||||
|
||||
dp_aclk: clock0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-accuracy = <100>;
|
||||
};
|
||||
|
||||
dp_aud_clk: clock1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
clock-accuracy = <100>;
|
||||
};
|
||||
|
||||
dpdma_clk: dpdma_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0x0>;
|
||||
clock-frequency = <533000000>;
|
||||
};
|
||||
|
||||
drm_clock: drm_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0x0>;
|
||||
clock-frequency = <262750000>;
|
||||
clock-accuracy = <0x64>;
|
||||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&can1 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan1 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan2 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan3 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan4 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan5 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan6 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan7 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan8 {
|
||||
clocks = <&clk600>, <&clk100>;
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
clocks = <&clk125>, <&clk125>, <&clk125>;
|
||||
};
|
||||
|
||||
&gem1 {
|
||||
clocks = <&clk125>, <&clk125>, <&clk125>;
|
||||
};
|
||||
|
||||
&gem2 {
|
||||
clocks = <&clk125>, <&clk125>, <&clk125>;
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
clocks = <&clk125>, <&clk125>, <&clk125>;
|
||||
};
|
||||
|
||||
&gpio {
|
||||
clocks = <&clk100>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clocks = <&clk100>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clocks = <&clk100>;
|
||||
};
|
||||
|
||||
&sata {
|
||||
clocks = <&clk250>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
clocks = <&clk200 &clk200>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
clocks = <&clk200 &clk200>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
clocks = <&clk200 &clk200>;
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
clocks = <&clk200 &clk200>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
clocks = <&clk250>, <&clk250>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
clocks = <&clk250>, <&clk250>;
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
clocks = <&clk250>;
|
||||
};
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* clock specification for Xilinx ZynqMP ep108 development board
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ep108 development board
|
||||
*
|
||||
|
|
@ -47,7 +48,7 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@0{
|
||||
phy0: phy@0 {
|
||||
reg = <0>;
|
||||
max-speed = <100>;
|
||||
};
|
||||
|
|
@ -78,10 +79,20 @@
|
|||
&sata {
|
||||
status = "okay";
|
||||
ceva,broken-gen2;
|
||||
/* SATA Phy OOB timing settings */
|
||||
ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
|
||||
ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
|
||||
ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
|
||||
ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
|
||||
ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,54 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZC1232
|
||||
*
|
||||
* (C) Copyright 2017 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZC1232 RevA";
|
||||
compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &dcc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
/* SATA OOB timing settings */
|
||||
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZC1254
|
||||
*
|
||||
* (C) Copyright 2015 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZC1254 RevA";
|
||||
compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &dcc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZC1275
|
||||
*
|
||||
* (C) Copyright 2017 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZC1275 RevA";
|
||||
compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &dcc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
|
||||
*
|
||||
* (C) Copyright 2015 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP zc1751-xm015-dc1 RevA";
|
||||
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem3;
|
||||
i2c0 = &i2c1;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
eeprom: eeprom@55 {
|
||||
compatible = "atmel,24c64"; /* 24AA64 */
|
||||
reg = <0x55>;
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
/* SATA phy OOB timing settings */
|
||||
ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
|
||||
ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
|
||||
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,168 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
|
||||
*
|
||||
* (C) Copyright 2015 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP zc1751-xm016-dc2 RevA";
|
||||
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
can0 = &can0;
|
||||
can1 = &can1;
|
||||
ethernet0 = &gem2;
|
||||
i2c0 = &i2c0;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
spi0 = &spi0;
|
||||
spi1 = &spi1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem2 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@5 {
|
||||
reg = <5>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tca6416_u26: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
/* IRQ not connected */
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
|
||||
spi0_flash0: flash0@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25wf080", "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
|
||||
partition@0 {
|
||||
label = "data";
|
||||
reg = <0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
|
||||
spi1_flash0: flash0@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
|
||||
partition@0 {
|
||||
label = "data";
|
||||
reg = <0x0 0x84000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm017-dc3
|
||||
*
|
||||
* (C) Copyright 2016 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP zc1751-xm017-dc3 RevA";
|
||||
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem0;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@0 { /* VSC8211 */
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* just eeprom here */
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tca6416_u26: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
/* IRQ not connected */
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eeprom24c02 and SE98A temp chip pca9306 */
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
/* SATA phy OOB timing settings */
|
||||
ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
|
||||
ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
|
||||
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
};
|
||||
|
||||
&sdhci1 { /* emmc with some settings */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* main */
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* DB9 */
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
@ -0,0 +1,178 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm018-dc4
|
||||
*
|
||||
* (C) Copyright 2015 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP zc1751-xm018-dc4";
|
||||
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem0;
|
||||
ethernet1 = &gem1;
|
||||
ethernet2 = &gem2;
|
||||
ethernet3 = &gem3;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðernet_phy0>;
|
||||
ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
|
||||
reg = <0>;
|
||||
};
|
||||
ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
|
||||
reg = <7>;
|
||||
};
|
||||
ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
|
||||
reg = <3>;
|
||||
};
|
||||
ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
|
||||
reg = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&gem1 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðernet_phy7>;
|
||||
};
|
||||
|
||||
&gem2 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðernet_phy3>;
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðernet_phy8>;
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
|
||||
*
|
||||
* (C) Copyright 2015 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP zc1751-xm019-dc5 RevA";
|
||||
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem1;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci0;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem1 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
&ttc0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ttc1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ttc2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ttc3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,289 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU100 revC
|
||||
*
|
||||
* (C) Copyright 2016 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Nathalie Chan King Choy
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZCU100 RevC";
|
||||
compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart0;
|
||||
serial2 = &dcc;
|
||||
spi0 = &spi0;
|
||||
spi1 = &spi1;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
autorepeat;
|
||||
sw4 {
|
||||
label = "sw4";
|
||||
gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
autorepeat;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
ds2 {
|
||||
label = "ds2";
|
||||
gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
ds3 {
|
||||
label = "ds3";
|
||||
gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "phy0tx"; /* WLAN tx */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
ds4 {
|
||||
label = "ds4";
|
||||
gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "phy0rx"; /* WLAN rx */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
ds5 {
|
||||
label = "ds5";
|
||||
gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "bluetooth-power";
|
||||
};
|
||||
|
||||
vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
|
||||
label = "vbus_det";
|
||||
gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
bt_power {
|
||||
label = "bt_power";
|
||||
gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
wmmcsdio_fixed: fixedregulator-mmcsdio {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "wmmcsdio_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio_pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
|
||||
"I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
|
||||
"SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
|
||||
"SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
|
||||
"PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
|
||||
"VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
|
||||
"DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
|
||||
"", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
|
||||
"GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
|
||||
"GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
|
||||
"SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
|
||||
"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
|
||||
"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
|
||||
"USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
|
||||
"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
|
||||
"USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
|
||||
"", "",
|
||||
"", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
i2c-mux@75 { /* u11 */
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
i2csw_0: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
label = "LS-I2C0";
|
||||
};
|
||||
i2csw_1: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
label = "LS-I2C1";
|
||||
};
|
||||
i2csw_2: i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
label = "HS-I2C2";
|
||||
};
|
||||
i2csw_3: i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
label = "HS-I2C3";
|
||||
};
|
||||
i2csw_4: i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x4>;
|
||||
|
||||
pmic: pmic@5e { /* Custom TI PMIC u33 */
|
||||
compatible = "ti,tps65086";
|
||||
reg = <0x5e>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <77 GPIO_ACTIVE_LOW>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
i2csw_5: i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
/* PS_PMBUS */
|
||||
ina226@40 { /* u35 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <10000>;
|
||||
/* MIO31 is alert which should be routed to PMUFW */
|
||||
};
|
||||
};
|
||||
i2csw_6: i2c@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
/*
|
||||
* Not Connected
|
||||
*/
|
||||
};
|
||||
i2csw_7: i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
/*
|
||||
* usb5744 (DNP) - U5
|
||||
* 100kHz - this is default freq for us
|
||||
*/
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SD0 only supports 3.3V, no level shifter */
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
broken-cd; /* CD has to be enabled by default */
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
bus-width = <0x4>;
|
||||
non-removable;
|
||||
disable-wp;
|
||||
cap-power-off-card;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
vqmmc-supply = <&wmmcsdio_fixed>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
wlcore: wifi@2 {
|
||||
compatible = "ti,wl1831";
|
||||
reg = <2>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 { /* Low Speed connector */
|
||||
status = "okay";
|
||||
label = "LS-SPI0";
|
||||
};
|
||||
|
||||
&spi1 { /* High Speed connector */
|
||||
status = "okay";
|
||||
label = "HS-SPI1";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU102 Rev1.0
|
||||
*
|
||||
* (C) Copyright 2016 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
#include "zynqmp-zcu102-revB.dts"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZCU102 Rev1.0";
|
||||
compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
|
||||
};
|
||||
|
||||
&eeprom {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
board_sn: board-sn@0 {
|
||||
reg = <0x0 0x14>;
|
||||
};
|
||||
|
||||
eth_mac: eth-mac@20 {
|
||||
reg = <0x20 0x6>;
|
||||
};
|
||||
|
||||
board_name: board-name@d0 {
|
||||
reg = <0xd0 0x6>;
|
||||
};
|
||||
|
||||
board_revision: board-revision@e0 {
|
||||
reg = <0xe0 0x3>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,548 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU102 RevA
|
||||
*
|
||||
* (C) Copyright 2015 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZCU102 RevA";
|
||||
compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem3;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &dcc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
autorepeat;
|
||||
sw19 {
|
||||
label = "sw19";
|
||||
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_DOWN>;
|
||||
gpio-key,wakeup;
|
||||
autorepeat;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
heartbeat_led {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@21 {
|
||||
reg = <21>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tca6416_u97: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
/*
|
||||
* IRQ not connected
|
||||
* Lines:
|
||||
* 0 - PS_GTR_LAN_SEL0
|
||||
* 1 - PS_GTR_LAN_SEL1
|
||||
* 2 - PS_GTR_LAN_SEL2
|
||||
* 3 - PS_GTR_LAN_SEL3
|
||||
* 4 - PCI_CLK_DIR_SEL
|
||||
* 5 - IIC_MUX_RESET_B
|
||||
* 6 - GEM3_EXP_RESET_B
|
||||
* 7, 10 - 17 - not connected
|
||||
*/
|
||||
|
||||
gtr_sel0 {
|
||||
gpio-hog;
|
||||
gpios = <0 0>;
|
||||
output-low; /* PCIE = 0, DP = 1 */
|
||||
line-name = "sel0";
|
||||
};
|
||||
gtr_sel1 {
|
||||
gpio-hog;
|
||||
gpios = <1 0>;
|
||||
output-high; /* PCIE = 0, DP = 1 */
|
||||
line-name = "sel1";
|
||||
};
|
||||
gtr_sel2 {
|
||||
gpio-hog;
|
||||
gpios = <2 0>;
|
||||
output-high; /* PCIE = 0, USB0 = 1 */
|
||||
line-name = "sel2";
|
||||
};
|
||||
gtr_sel3 {
|
||||
gpio-hog;
|
||||
gpios = <3 0>;
|
||||
output-high; /* PCIE = 0, SATA = 1 */
|
||||
line-name = "sel3";
|
||||
};
|
||||
};
|
||||
|
||||
tca6416_u61: gpio@21 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
/*
|
||||
* IRQ not connected
|
||||
* Lines:
|
||||
* 0 - VCCPSPLL_EN
|
||||
* 1 - MGTRAVCC_EN
|
||||
* 2 - MGTRAVTT_EN
|
||||
* 3 - VCCPSDDRPLL_EN
|
||||
* 4 - MIO26_PMU_INPUT_LS
|
||||
* 5 - PL_PMBUS_ALERT
|
||||
* 6 - PS_PMBUS_ALERT
|
||||
* 7 - MAXIM_PMBUS_ALERT
|
||||
* 10 - PL_DDR4_VTERM_EN
|
||||
* 11 - PL_DDR4_VPP_2V5_EN
|
||||
* 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
|
||||
* 13 - PS_DIMM_SUSPEND_EN
|
||||
* 14 - PS_DDR4_VTERM_EN
|
||||
* 15 - PS_DDR4_VPP_2V5_EN
|
||||
* 16 - 17 - not connected
|
||||
*/
|
||||
};
|
||||
|
||||
i2c-mux@75 { /* u60 */
|
||||
compatible = "nxp,pca9544";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* PS_PMBUS */
|
||||
ina226@40 { /* u76 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@41 { /* u77 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u78 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u87 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@44 { /* u85 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u86 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u93 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@47 { /* u88 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4a { /* u15 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x4a>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4b { /* u92 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x4b>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
};
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* PL_PMBUS */
|
||||
ina226@40 { /* u79 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
ina226@41 { /* u81 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u80 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u84 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@44 { /* u16 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u65 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u74 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@47 { /* u75 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
/* MAXIM_PMBUS - 00 */
|
||||
max15301@a { /* u46 */
|
||||
compatible = "maxim,max15301";
|
||||
reg = <0xa>;
|
||||
};
|
||||
max15303@b { /* u4 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0xb>;
|
||||
};
|
||||
max15303@10 { /* u13 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x10>;
|
||||
};
|
||||
max15301@13 { /* u47 */
|
||||
compatible = "maxim,max15301";
|
||||
reg = <0x13>;
|
||||
};
|
||||
max15303@14 { /* u7 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x14>;
|
||||
};
|
||||
max15303@15 { /* u6 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x15>;
|
||||
};
|
||||
max15303@16 { /* u10 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x16>;
|
||||
};
|
||||
max15303@17 { /* u9 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x17>;
|
||||
};
|
||||
max15301@18 { /* u63 */
|
||||
compatible = "maxim,max15301";
|
||||
reg = <0x18>;
|
||||
};
|
||||
max15303@1a { /* u49 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
max15303@1d { /* u18 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x1d>;
|
||||
};
|
||||
max15303@20 { /* u8 */
|
||||
compatible = "maxim,max15303";
|
||||
status = "disabled"; /* unreachable */
|
||||
reg = <0x20>;
|
||||
};
|
||||
|
||||
max20751@72 { /* u95 */
|
||||
compatible = "maxim,max20751";
|
||||
reg = <0x72>;
|
||||
};
|
||||
max20751@73 { /* u96 */
|
||||
compatible = "maxim,max20751";
|
||||
reg = <0x73>;
|
||||
};
|
||||
};
|
||||
/* Bus 3 is not connected */
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
/* PL i2c via PCA9306 - u45 */
|
||||
i2c-mux@74 { /* u34 */
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/*
|
||||
* IIC_EEPROM 1kB memory which uses 256B blocks
|
||||
* where every block has different address.
|
||||
* 0 - 256B address 0x54
|
||||
* 256B - 512B address 0x55
|
||||
* 512B - 768B address 0x56
|
||||
* 768B - 1024B address 0x57
|
||||
*/
|
||||
eeprom: eeprom@54 { /* u23 */
|
||||
compatible = "atmel,24c08";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
si5341: clock-generator@36 { /* SI5341 - u69 */
|
||||
reg = <0x36>;
|
||||
};
|
||||
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
si570_1: clock-generator@5d { /* USER SI570 - u42 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <300000000>;
|
||||
clock-frequency = <300000000>;
|
||||
};
|
||||
};
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>; /* copy from zc702 */
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
};
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
si5328: clock-generator@69 {/* SI5328 - u20 */
|
||||
reg = <0x69>;
|
||||
/*
|
||||
* Chip has interrupt present connected to PL
|
||||
* interrupt-parent = <&>;
|
||||
* interrupts = <>;
|
||||
*/
|
||||
};
|
||||
};
|
||||
/* 5 - 7 unconnected */
|
||||
};
|
||||
|
||||
i2c-mux@75 {
|
||||
compatible = "nxp,pca9548"; /* u135 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* HPC0_IIC */
|
||||
};
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* HPC1_IIC */
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
/* SYSMON */
|
||||
};
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
/* DDR4 SODIMM */
|
||||
};
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
/* SEP 3 */
|
||||
};
|
||||
i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
/* SEP 2 */
|
||||
};
|
||||
i2c@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
/* SEP 1 */
|
||||
};
|
||||
i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
/* SEP 0 */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
/* SATA OOB timing settings */
|
||||
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
};
|
||||
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU102 RevB
|
||||
*
|
||||
* (C) Copyright 2016 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
#include "zynqmp-zcu102-revA.dts"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZCU102 RevB";
|
||||
compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
phy-handle = <&phyc>;
|
||||
phyc: phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
};
|
||||
/* Cleanup from RevA */
|
||||
/delete-node/ phy@21;
|
||||
};
|
||||
|
||||
/* Fix collision with u61 */
|
||||
&i2c0 {
|
||||
i2c-mux@75 {
|
||||
i2c@2 {
|
||||
max15303@1b { /* u8 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x1b>;
|
||||
};
|
||||
/delete-node/ max15303@20;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,195 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU104
|
||||
*
|
||||
* (C) Copyright 2017 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZCU104 RevA";
|
||||
compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem3;
|
||||
i2c0 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &dcc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
/* Another connection to this bus via PL i2c via PCA9306 - u45 */
|
||||
i2c-mux@74 { /* u34 */
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/*
|
||||
* IIC_EEPROM 1kB memory which uses 256B blocks
|
||||
* where every block has different address.
|
||||
* 0 - 256B address 0x54
|
||||
* 256B - 512B address 0x55
|
||||
* 512B - 768B address 0x56
|
||||
* 768B - 1024B address 0x57
|
||||
*/
|
||||
eeprom@54 { /* u23 */
|
||||
compatible = "atmel,24c08";
|
||||
reg = <0x54>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
|
||||
reg = <0x6c>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
|
||||
reg = <0x43>;
|
||||
};
|
||||
irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
|
||||
reg = <0x4d>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
tca6416_u97: gpio@21 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
/*
|
||||
* IRQ not connected
|
||||
* Lines:
|
||||
* 0 - IRPS5401_ALERT_B
|
||||
* 1 - HDMI_8T49N241_INT_ALM
|
||||
* 2 - MAX6643_OT_B
|
||||
* 3 - MAX6643_FANFAIL_B
|
||||
* 5 - IIC_MUX_RESET_B
|
||||
* 6 - GEM3_EXP_RESET_B
|
||||
* 7 - FMC_LPC_PRSNT_M2C_B
|
||||
* 4, 10 - 17 - not connected
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
};
|
||||
|
||||
i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
};
|
||||
|
||||
/* 3, 6 not connected */
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
/* SATA OOB timing settings */
|
||||
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
};
|
||||
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,522 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU106
|
||||
*
|
||||
* (C) Copyright 2016, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZCU106 RevA";
|
||||
compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem3;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &dcc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
autorepeat;
|
||||
sw19 {
|
||||
label = "sw19";
|
||||
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_DOWN>;
|
||||
gpio-key,wakeup;
|
||||
autorepeat;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
heartbeat_led {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tca6416_u97: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller; /* interrupt not connected */
|
||||
#gpio-cells = <2>;
|
||||
/*
|
||||
* IRQ not connected
|
||||
* Lines:
|
||||
* 0 - SFP_SI5328_INT_ALM
|
||||
* 1 - HDMI_SI5328_INT_ALM
|
||||
* 5 - IIC_MUX_RESET_B
|
||||
* 6 - GEM3_EXP_RESET_B
|
||||
* 10 - FMC_HPC0_PRSNT_M2C_B
|
||||
* 11 - FMC_HPC1_PRSNT_M2C_B
|
||||
* 2-4, 7, 12-17 - not connected
|
||||
*/
|
||||
};
|
||||
|
||||
tca6416_u61: gpio@21 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
/*
|
||||
* IRQ not connected
|
||||
* Lines:
|
||||
* 0 - VCCPSPLL_EN
|
||||
* 1 - MGTRAVCC_EN
|
||||
* 2 - MGTRAVTT_EN
|
||||
* 3 - VCCPSDDRPLL_EN
|
||||
* 4 - MIO26_PMU_INPUT_LS
|
||||
* 5 - PL_PMBUS_ALERT
|
||||
* 6 - PS_PMBUS_ALERT
|
||||
* 7 - MAXIM_PMBUS_ALERT
|
||||
* 10 - PL_DDR4_VTERM_EN
|
||||
* 11 - PL_DDR4_VPP_2V5_EN
|
||||
* 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
|
||||
* 13 - PS_DIMM_SUSPEND_EN
|
||||
* 14 - PS_DDR4_VTERM_EN
|
||||
* 15 - PS_DDR4_VPP_2V5_EN
|
||||
* 16 - 17 - not connected
|
||||
*/
|
||||
};
|
||||
|
||||
i2c-mux@75 { /* u60 */
|
||||
compatible = "nxp,pca9544";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* PS_PMBUS */
|
||||
ina226@40 { /* u76 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@41 { /* u77 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u78 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u87 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@44 { /* u85 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u86 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u93 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@47 { /* u88 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4a { /* u15 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x4a>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4b { /* u92 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x4b>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
};
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* PL_PMBUS */
|
||||
ina226@40 { /* u79 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
ina226@41 { /* u81 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u80 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u84 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@44 { /* u16 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u65 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u74 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@47 { /* u75 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
/* MAXIM_PMBUS - 00 */
|
||||
max15301@a { /* u46 */
|
||||
compatible = "maxim,max15301";
|
||||
reg = <0xa>;
|
||||
};
|
||||
max15303@b { /* u4 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0xb>;
|
||||
};
|
||||
max15303@10 { /* u13 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x10>;
|
||||
};
|
||||
max15301@13 { /* u47 */
|
||||
compatible = "maxim,max15301";
|
||||
reg = <0x13>;
|
||||
};
|
||||
max15303@14 { /* u7 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x14>;
|
||||
};
|
||||
max15303@15 { /* u6 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x15>;
|
||||
};
|
||||
max15303@16 { /* u10 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x16>;
|
||||
};
|
||||
max15303@17 { /* u9 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x17>;
|
||||
};
|
||||
max15301@18 { /* u63 */
|
||||
compatible = "maxim,max15301";
|
||||
reg = <0x18>;
|
||||
};
|
||||
max15303@1a { /* u49 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
max15303@1b { /* u8 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x1b>;
|
||||
};
|
||||
max15303@1d { /* u18 */
|
||||
compatible = "maxim,max15303";
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
max20751@72 { /* u95 */
|
||||
compatible = "maxim,max20751";
|
||||
reg = <0x72>;
|
||||
};
|
||||
max20751@73 { /* u96 */
|
||||
compatible = "maxim,max20751";
|
||||
reg = <0x73>;
|
||||
};
|
||||
};
|
||||
/* Bus 3 is not connected */
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
/* PL i2c via PCA9306 - u45 */
|
||||
i2c-mux@74 { /* u34 */
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/*
|
||||
* IIC_EEPROM 1kB memory which uses 256B blocks
|
||||
* where every block has different address.
|
||||
* 0 - 256B address 0x54
|
||||
* 256B - 512B address 0x55
|
||||
* 512B - 768B address 0x56
|
||||
* 768B - 1024B address 0x57
|
||||
*/
|
||||
eeprom: eeprom@54 { /* u23 */
|
||||
compatible = "atmel,24c08";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
si5341: clock-generator@36 { /* SI5341 - u69 */
|
||||
reg = <0x36>;
|
||||
};
|
||||
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
si570_1: clock-generator@5d { /* USER SI570 - u42 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <300000000>;
|
||||
clock-frequency = <300000000>;
|
||||
};
|
||||
};
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>; /* copy from zc702 */
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
};
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
si5328: clock-generator@69 {/* SI5328 - u20 */
|
||||
reg = <0x69>;
|
||||
};
|
||||
};
|
||||
i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>; /* FAN controller */
|
||||
temp@4c {/* lm96163 - u128 */
|
||||
compatible = "national,lm96163";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
/* 6 - 7 unconnected */
|
||||
};
|
||||
|
||||
i2c-mux@75 {
|
||||
compatible = "nxp,pca9548"; /* u135 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* HPC0_IIC */
|
||||
};
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* HPC1_IIC */
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
/* SYSMON */
|
||||
};
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
/* DDR4 SODIMM */
|
||||
};
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
/* SEP 3 */
|
||||
};
|
||||
i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
/* SEP 2 */
|
||||
};
|
||||
i2c@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
/* SEP 1 */
|
||||
};
|
||||
i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
/* SEP 0 */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
/* SATA OOB timing settings */
|
||||
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
};
|
||||
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,444 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU111
|
||||
*
|
||||
* (C) Copyright 2017 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZCU111 RevA";
|
||||
compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem3;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &dcc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
/* Another 4GB connected to PL */
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
autorepeat;
|
||||
sw19 {
|
||||
label = "sw19";
|
||||
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_DOWN>;
|
||||
gpio-key,wakeup;
|
||||
autorepeat;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
heartbeat_led {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tca6416_u22: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller; /* interrupt not connected */
|
||||
#gpio-cells = <2>;
|
||||
/*
|
||||
* IRQ not connected
|
||||
* Lines:
|
||||
* 0 - MAX6643_OT_B
|
||||
* 1 - MAX6643_FANFAIL_B
|
||||
* 2 - MIO26_PMU_INPUT_LS
|
||||
* 4 - SFP_SI5382_INT_ALM
|
||||
* 5 - IIC_MUX_RESET_B
|
||||
* 6 - GEM3_EXP_RESET_B
|
||||
* 10 - FMCP_HSPC_PRSNT_M2C_B
|
||||
* 11 - CLK_SPI_MUX_SEL0
|
||||
* 12 - CLK_SPI_MUX_SEL1
|
||||
* 16 - IRPS5401_ALERT_B
|
||||
* 17 - INA226_PMBUS_ALERT
|
||||
* 3, 7, 13-15 - not connected
|
||||
*/
|
||||
};
|
||||
|
||||
i2c-mux@75 { /* u23 */
|
||||
compatible = "nxp,pca9544";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* PS_PMBUS */
|
||||
/* PMBUS_ALERT done via pca9544 */
|
||||
ina226@40 { /* u67 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
ina226@41 { /* u59 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u61 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u60 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u64 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u69 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
ina226@47 { /* u66 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@48 { /* u65 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x48>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@49 { /* u63 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x49>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4a { /* u3 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x4a>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4b { /* u71 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x4b>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4c { /* u77 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x4c>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4d { /* u73 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x4d>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4e { /* u79 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x4e>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
};
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* NC */
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
|
||||
reg = <0x43>;
|
||||
};
|
||||
irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
|
||||
reg = <0x44>;
|
||||
};
|
||||
irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
|
||||
reg = <0x45>;
|
||||
};
|
||||
/* u68 IR38064 +0 */
|
||||
/* u70 IR38060 +1 */
|
||||
/* u74 IR38060 +2 */
|
||||
/* u75 IR38060 +6 */
|
||||
/* J19 header too */
|
||||
|
||||
};
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
/* SYSMON */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
i2c-mux@74 { /* u26 */
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/*
|
||||
* IIC_EEPROM 1kB memory which uses 256B blocks
|
||||
* where every block has different address.
|
||||
* 0 - 256B address 0x54
|
||||
* 256B - 512B address 0x55
|
||||
* 512B - 768B address 0x56
|
||||
* 768B - 1024B address 0x57
|
||||
*/
|
||||
eeprom: eeprom@54 { /* u88 */
|
||||
compatible = "atmel,24c08";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
si5341: clock-generator@36 { /* SI5341 - u46 */
|
||||
reg = <0x36>;
|
||||
};
|
||||
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
si570_1: clock-generator@5d { /* USER SI570 - u47 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <300000000>;
|
||||
clock-frequency = <300000000>;
|
||||
};
|
||||
};
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
};
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
si5328: clock-generator@69 { /* SI5328 - u48 */
|
||||
reg = <0x69>;
|
||||
};
|
||||
};
|
||||
i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
sc18is603@2f { /* sc18is602 - u93 */
|
||||
compatible = "nxp,sc18is603";
|
||||
reg = <0x2f>;
|
||||
/* 4 gpios for CS not handled by driver */
|
||||
/*
|
||||
* USB2ANY cable or
|
||||
* LMK04208 - u90 or
|
||||
* LMX2594 - u102 or
|
||||
* LMX2594 - u103 or
|
||||
* LMX2594 - u104
|
||||
*/
|
||||
};
|
||||
};
|
||||
i2c@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
/* FMC connector */
|
||||
};
|
||||
/* 7 NC */
|
||||
};
|
||||
|
||||
i2c-mux@75 {
|
||||
compatible = "nxp,pca9548"; /* u27 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* FMCP_HSPC_IIC */
|
||||
};
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* NC */
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
/* SYSMON */
|
||||
};
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
/* DDR4 SODIMM */
|
||||
};
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
/* SFP3 */
|
||||
};
|
||||
i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
/* SFP2 */
|
||||
};
|
||||
i2c@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
/* SFP1 */
|
||||
};
|
||||
i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
/* SFP0 */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
/* SATA OOB timing settings */
|
||||
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
};
|
||||
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP
|
||||
*
|
||||
|
|
@ -355,7 +356,7 @@
|
|||
};
|
||||
|
||||
gem0: ethernet@ff0b0000 {
|
||||
compatible = "cdns,gem";
|
||||
compatible = "cdns,zynqmp-gem", "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 57 4>, <0 57 4>;
|
||||
|
|
@ -366,7 +367,7 @@
|
|||
};
|
||||
|
||||
gem1: ethernet@ff0c0000 {
|
||||
compatible = "cdns,gem";
|
||||
compatible = "cdns,zynqmp-gem", "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 59 4>, <0 59 4>;
|
||||
|
|
@ -377,7 +378,7 @@
|
|||
};
|
||||
|
||||
gem2: ethernet@ff0d0000 {
|
||||
compatible = "cdns,gem";
|
||||
compatible = "cdns,zynqmp-gem", "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 61 4>, <0 61 4>;
|
||||
|
|
@ -388,7 +389,7 @@
|
|||
};
|
||||
|
||||
gem3: ethernet@ff0e0000 {
|
||||
compatible = "cdns,gem";
|
||||
compatible = "cdns,zynqmp-gem", "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 63 4>, <0 63 4>;
|
||||
|
|
@ -439,10 +440,10 @@
|
|||
device_type = "pci";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 118 4>,
|
||||
<0 117 4>,
|
||||
<0 116 4>,
|
||||
<0 115 4>, /* MSI_1 [63...32] */
|
||||
<0 114 4>; /* MSI_0 [31...0] */
|
||||
<0 117 4>,
|
||||
<0 116 4>,
|
||||
<0 115 4>, /* MSI_1 [63...32] */
|
||||
<0 114 4>; /* MSI_0 [31...0] */
|
||||
interrupt-names = "misc", "dummy", "intx",
|
||||
"msi1", "msi0";
|
||||
msi-parent = <&pcie>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue