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MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.h 

We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove
it to mach-cavium-octeon/cpu-feature-overrides.h

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney 2009-05-13 15:59:56 -07:00 committed by Ralf Baechle
parent fbeda19f82
commit 4bb1a1089e
2 changed files with 1 additions and 4 deletions
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1
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
View File

@ -53,6 +53,7 @@
#define cpu_has_userlocal 0 #define cpu_has_userlocal 0
#define cpu_has_vint 0 #define cpu_has_vint 0
#define cpu_has_veic 0 #define cpu_has_veic 0
#define cpu_hwrena_impl_bits 0xc0000000
#define ARCH_HAS_READ_CURRENT_TIMER 1 #define ARCH_HAS_READ_CURRENT_TIMER 1
#define ARCH_HAS_IRQ_PER_CPU 1 #define ARCH_HAS_IRQ_PER_CPU 1
#define ARCH_HAS_SPINLOCK_PREFETCH 1 #define ARCH_HAS_SPINLOCK_PREFETCH 1

4
arch/mips/kernel/traps.c
View File

@ -1510,10 +1510,6 @@ void __cpuinit per_cpu_trap_init(void)
write_c0_hwrena(enable); write_c0_hwrena(enable);
} }
#ifdef CONFIG_CPU_CAVIUM_OCTEON
write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */
#endif
#ifdef CONFIG_MIPS_MT_SMTC #ifdef CONFIG_MIPS_MT_SMTC
if (!secondaryTC) { if (!secondaryTC) {
#endif /* CONFIG_MIPS_MT_SMTC */ #endif /* CONFIG_MIPS_MT_SMTC */