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ARM: dts: r8a7792: add PLL1 divided by 2 clock 

Despite the fact that QSPI clock has PLL1/VCOx1/4 clock as a parent, the
latter hasn't been added to the R8A7792 device tree. This patch corrects
that oversight.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Sergei Shtylyov 2016-07-12 00:51:58 +03:00 committed by Simon Horman
parent 8fd763c75c
commit 4b9b7b3a2c
1 changed files with 7 additions and 0 deletions
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7
arch/arm/boot/dts/r8a7792.dtsi
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@ -284,6 +284,13 @@
}; };
/* Fixed factor clocks */ /* Fixed factor clocks */
pll1_div2_clk: pll1_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
};
zs_clk: zs { zs_clk: zs {
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>; clocks = <&cpg_clocks R8A7792_CLK_PLL1>;