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net/mlx5: Make get_cqe routine not ethernet-specific 

Move mlx5e_get_cqe routine to wq.h and rename it to
mlx5_cqwq_get_cqe.

This allows it to be used by other CQ users outside of the
ethernet driver code.

A later patch in this patchset will make use of it from
FPGA code for the FPGA high-speed connection.

Signed-off-by: Ilan Tayari <ilant@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
This commit is contained in:
Ilan Tayari 2017-06-19 12:53:25 +03:00 committed by Saeed Mahameed
parent 095b0927f0
commit 4b67379376
5 changed files with 21 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/net/ethernet/mellanox/mlx5/core/en.h
View File

@ -833,7 +833,6 @@ void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq); void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq);
void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
void mlx5e_rx_am(struct mlx5e_rq *rq); void mlx5e_rx_am(struct mlx5e_rq *rq);
void mlx5e_rx_am_work(struct work_struct *work); void mlx5e_rx_am_work(struct work_struct *work);

4
drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
View File

@ -996,7 +996,7 @@ int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
for (; work_done < budget; work_done++) { for (; work_done < budget; work_done++) {
struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq); struct mlx5_cqe64 *cqe = mlx5_cqwq_get_cqe(&cq->wq);
if (!cqe) if (!cqe)
break; break;
@ -1050,7 +1050,7 @@ bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
u16 wqe_counter; u16 wqe_counter;
bool last_wqe; bool last_wqe;
cqe = mlx5e_get_cqe(cq); cqe = mlx5_cqwq_get_cqe(&cq->wq);
if (!cqe) if (!cqe)
break; break;

2
drivers/net/ethernet/mellanox/mlx5/core/en_tx.c
View File

@ -409,7 +409,7 @@ bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
u16 wqe_counter; u16 wqe_counter;
bool last_wqe; bool last_wqe;
cqe = mlx5e_get_cqe(cq); cqe = mlx5_cqwq_get_cqe(&cq->wq);
if (!cqe) if (!cqe)
break; break;

19
drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c
View File

@ -32,23 +32,6 @@
#include "en.h" #include "en.h"
struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq)
{
struct mlx5_cqwq *wq = &cq->wq;
u32 ci = mlx5_cqwq_get_ci(wq);
struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
u8 cqe_ownership_bit = cqe->op_own & MLX5_CQE_OWNER_MASK;
u8 sw_ownership_val = mlx5_cqwq_get_wrap_cnt(wq) & 1;
if (cqe_ownership_bit != sw_ownership_val)
return NULL;
/* ensure cqe content is read after cqe ownership bit */
dma_rmb();
return cqe;
}
static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq, static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
struct mlx5e_icosq *sq, struct mlx5e_icosq *sq,
struct mlx5_cqe64 *cqe, struct mlx5_cqe64 *cqe,
@ -89,7 +72,7 @@ static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))) if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
return; return;
cqe = mlx5e_get_cqe(cq); cqe = mlx5_cqwq_get_cqe(&cq->wq);
if (likely(!cqe)) if (likely(!cqe))
return; return;

17
drivers/net/ethernet/mellanox/mlx5/core/wq.h
View File

@ -34,6 +34,7 @@
#define __MLX5_WQ_H__ #define __MLX5_WQ_H__
#include <linux/mlx5/mlx5_ifc.h> #include <linux/mlx5/mlx5_ifc.h>
#include <linux/mlx5/cq.h>
struct mlx5_wq_param { struct mlx5_wq_param {
int linear; int linear;
@ -146,6 +147,22 @@ static inline void mlx5_cqwq_update_db_record(struct mlx5_cqwq *wq)
*wq->db = cpu_to_be32(wq->cc & 0xffffff); *wq->db = cpu_to_be32(wq->cc & 0xffffff);
} }
static inline struct mlx5_cqe64 *mlx5_cqwq_get_cqe(struct mlx5_cqwq *wq)
{
u32 ci = mlx5_cqwq_get_ci(wq);
struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
u8 cqe_ownership_bit = cqe->op_own & MLX5_CQE_OWNER_MASK;
u8 sw_ownership_val = mlx5_cqwq_get_wrap_cnt(wq) & 1;
if (cqe_ownership_bit != sw_ownership_val)
return NULL;
/* ensure cqe content is read after cqe ownership bit */
dma_rmb();
return cqe;
}
static inline int mlx5_wq_ll_is_full(struct mlx5_wq_ll *wq) static inline int mlx5_wq_ll_is_full(struct mlx5_wq_ll *wq)
{ {
return wq->cur_sz == wq->sz_m1; return wq->cur_sz == wq->sz_m1;