phy: sun4i-usb: Support A83T USB PHYs
The A83T has 3 USB PHYs, 1 for OTG, 1 for standard USB, 1 for USB HSIC. The phy initialization procedure is very different from other SoCs, but the PMU bits are the same, with additional bits for HSIC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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@ -87,6 +87,16 @@
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#define PHY_DISCON_TH_SEL 0x2a
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#define PHY_SQUELCH_DETECT 0x3c
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/* A83T specific control bits for PHY0 */
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#define PHY_CTL_VBUSVLDEXT BIT(5)
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#define PHY_CTL_SIDDQ BIT(3)
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/* A83T specific control bits for PHY2 HSIC */
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#define SUNXI_EHCI_HS_FORCE BIT(20)
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#define SUNXI_HSIC_CONNECT_DET BIT(17)
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#define SUNXI_HSIC_CONNECT_INT BIT(16)
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#define SUNXI_HSIC BIT(1)
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#define MAX_PHYS 4
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/*
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@ -100,6 +110,7 @@ enum sun4i_usb_phy_type {
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sun4i_a10_phy,
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sun6i_a31_phy,
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sun8i_a33_phy,
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sun8i_a83t_phy,
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sun8i_h3_phy,
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sun8i_v3s_phy,
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sun50i_a64_phy,
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@ -234,6 +245,7 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
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static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
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{
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struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
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u32 bits, reg_value;
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if (!phy->pmu)
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@ -242,6 +254,11 @@ static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
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bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
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SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
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/* A83T USB2 is HSIC */
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if (phy_data->cfg->type == sun8i_a83t_phy && phy->index == 2)
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bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
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SUNXI_HSIC;
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reg_value = readl(phy->pmu);
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if (enable)
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@ -276,22 +293,31 @@ static int sun4i_usb_phy_init(struct phy *_phy)
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return ret;
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}
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if (phy->pmu && data->cfg->enable_pmu_unk1) {
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val = readl(phy->pmu + REG_PMU_UNK1);
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writel(val & ~2, phy->pmu + REG_PMU_UNK1);
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if (data->cfg->type == sun8i_a83t_phy) {
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if (phy->index == 0) {
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val = readl(data->base + data->cfg->phyctl_offset);
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val |= PHY_CTL_VBUSVLDEXT;
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val &= ~PHY_CTL_SIDDQ;
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writel(val, data->base + data->cfg->phyctl_offset);
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}
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} else {
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if (phy->pmu && data->cfg->enable_pmu_unk1) {
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val = readl(phy->pmu + REG_PMU_UNK1);
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writel(val & ~2, phy->pmu + REG_PMU_UNK1);
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}
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/* Enable USB 45 Ohm resistor calibration */
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if (phy->index == 0)
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sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
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/* Adjust PHY's magnitude and rate */
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sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
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/* Disconnect threshold adjustment */
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sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
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data->cfg->disc_thresh, 2);
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}
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/* Enable USB 45 Ohm resistor calibration */
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if (phy->index == 0)
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sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
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/* Adjust PHY's magnitude and rate */
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sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
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/* Disconnect threshold adjustment */
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sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
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data->cfg->disc_thresh, 2);
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sun4i_usb_phy_passby(phy, 1);
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if (phy->index == 0) {
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@ -316,6 +342,13 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
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struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
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if (phy->index == 0) {
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if (data->cfg->type == sun8i_a83t_phy) {
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void __iomem *phyctl = data->base +
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data->cfg->phyctl_offset;
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writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
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}
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/* Disable pull-ups */
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sun4i_usb_phy0_update_iscr(_phy, ISCR_DPDM_PULLUP_EN, 0);
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sun4i_usb_phy0_update_iscr(_phy, ISCR_ID_PULLUP_EN, 0);
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@ -868,6 +901,14 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
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.enable_pmu_unk1 = false,
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};
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static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
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.num_phys = 3,
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.hsic_index = 2,
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.type = sun8i_a83t_phy,
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.phyctl_offset = REG_PHYCTL_A33,
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.dedicated_clocks = true,
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};
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static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
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.num_phys = 4,
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.type = sun8i_h3_phy,
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@ -904,6 +945,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
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{ .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg },
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{ .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
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{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
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{ .compatible = "allwinner,sun8i-a83t-usb-phy", .data = &sun8i_a83t_cfg },
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{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
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{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
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{ .compatible = "allwinner,sun50i-a64-usb-phy",
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