irq_work, smp: Allow irq_work on call_single_queue
Currently irq_work_queue_on() will issue an unconditional arch_send_call_function_single_ipi() and has the handler do irq_work_run(). This is unfortunate in that it makes the IPI handler look at a second cacheline and it misses the opportunity to avoid the IPI. Instead note that struct irq_work and struct __call_single_data are very similar in layout, so use a few bits in the flags word to encode a type and stick the irq_work on the call_single_queue list. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20200526161908.011635912@infradead.org
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4b44a21dd6
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@ -13,6 +13,8 @@
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* busy NULL, 2 -> {free, claimed} : callback in progress, can be claimed
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*/
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/* flags share CSD_FLAG_ space */
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#define IRQ_WORK_PENDING BIT(0)
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#define IRQ_WORK_BUSY BIT(1)
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@ -23,9 +25,12 @@
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#define IRQ_WORK_CLAIMED (IRQ_WORK_PENDING | IRQ_WORK_BUSY)
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/*
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* structure shares layout with single_call_data_t.
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*/
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struct irq_work {
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atomic_t flags;
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struct llist_node llnode;
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atomic_t flags;
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void (*func)(struct irq_work *);
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};
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@ -16,17 +16,38 @@
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typedef void (*smp_call_func_t)(void *info);
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typedef bool (*smp_cond_func_t)(int cpu, void *info);
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enum {
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CSD_FLAG_LOCK = 0x01,
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/* IRQ_WORK_flags */
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CSD_TYPE_ASYNC = 0x00,
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CSD_TYPE_SYNC = 0x10,
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CSD_TYPE_IRQ_WORK = 0x20,
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CSD_FLAG_TYPE_MASK = 0xF0,
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};
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/*
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* structure shares (partial) layout with struct irq_work
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*/
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struct __call_single_data {
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struct llist_node llist;
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unsigned int flags;
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smp_call_func_t func;
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void *info;
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unsigned int flags;
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};
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/* Use __aligned() to avoid to use 2 cache lines for 1 csd */
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typedef struct __call_single_data call_single_data_t
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__aligned(sizeof(struct __call_single_data));
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/*
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* Enqueue a llist_node on the call_single_queue; be very careful, read
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* flush_smp_call_function_queue() in detail.
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*/
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extern void __smp_call_single_queue(int cpu, struct llist_node *node);
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/* total number of cpus in this system (may exceed NR_CPUS) */
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extern unsigned int total_cpus;
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@ -31,7 +31,7 @@ static bool irq_work_claim(struct irq_work *work)
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{
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int oflags;
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oflags = atomic_fetch_or(IRQ_WORK_CLAIMED, &work->flags);
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oflags = atomic_fetch_or(IRQ_WORK_CLAIMED | CSD_TYPE_IRQ_WORK, &work->flags);
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/*
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* If the work is already pending, no need to raise the IPI.
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* The pairing atomic_fetch_andnot() in irq_work_run() makes sure
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@ -102,8 +102,7 @@ bool irq_work_queue_on(struct irq_work *work, int cpu)
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if (cpu != smp_processor_id()) {
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/* Arch remote IPI send/receive backend aren't NMI safe */
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WARN_ON_ONCE(in_nmi());
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if (llist_add(&work->llnode, &per_cpu(raised_list, cpu)))
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arch_send_call_function_single_ipi(cpu);
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__smp_call_single_queue(cpu, &work->llnode);
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} else {
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__irq_work_queue_local(work);
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}
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@ -131,6 +130,31 @@ bool irq_work_needs_cpu(void)
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return true;
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}
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void irq_work_single(void *arg)
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{
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struct irq_work *work = arg;
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int flags;
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/*
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* Clear the PENDING bit, after this point the @work
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* can be re-used.
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* Make it immediately visible so that other CPUs trying
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* to claim that work don't rely on us to handle their data
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* while we are in the middle of the func.
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*/
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flags = atomic_fetch_andnot(IRQ_WORK_PENDING, &work->flags);
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lockdep_irq_work_enter(work);
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work->func(work);
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lockdep_irq_work_exit(work);
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/*
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* Clear the BUSY bit and return to the free state if
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* no-one else claimed it meanwhile.
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*/
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flags &= ~IRQ_WORK_PENDING;
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(void)atomic_cmpxchg(&work->flags, flags, flags & ~IRQ_WORK_BUSY);
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}
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static void irq_work_run_list(struct llist_head *list)
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{
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struct irq_work *work, *tmp;
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@ -142,27 +166,8 @@ static void irq_work_run_list(struct llist_head *list)
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return;
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llnode = llist_del_all(list);
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llist_for_each_entry_safe(work, tmp, llnode, llnode) {
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int flags;
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/*
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* Clear the PENDING bit, after this point the @work
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* can be re-used.
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* Make it immediately visible so that other CPUs trying
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* to claim that work don't rely on us to handle their data
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* while we are in the middle of the func.
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*/
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flags = atomic_fetch_andnot(IRQ_WORK_PENDING, &work->flags);
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lockdep_irq_work_enter(work);
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work->func(work);
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lockdep_irq_work_exit(work);
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/*
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* Clear the BUSY bit and return to the free state if
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* no-one else claimed it meanwhile.
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*/
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flags &= ~IRQ_WORK_PENDING;
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(void)atomic_cmpxchg(&work->flags, flags, flags & ~IRQ_WORK_BUSY);
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}
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llist_for_each_entry_safe(work, tmp, llnode, llnode)
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irq_work_single(work);
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}
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/*
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119
kernel/smp.c
119
kernel/smp.c
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@ -23,10 +23,8 @@
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#include "smpboot.h"
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enum {
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CSD_FLAG_LOCK = 0x01,
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CSD_FLAG_SYNCHRONOUS = 0x02,
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};
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#define CSD_TYPE(_csd) ((_csd)->flags & CSD_FLAG_TYPE_MASK)
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struct call_function_data {
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call_single_data_t __percpu *csd;
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@ -137,15 +135,33 @@ static DEFINE_PER_CPU_SHARED_ALIGNED(call_single_data_t, csd_data);
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extern void send_call_function_single_ipi(int cpu);
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void __smp_call_single_queue(int cpu, struct llist_node *node)
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{
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/*
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* The list addition should be visible before sending the IPI
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* handler locks the list to pull the entry off it because of
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* normal cache coherency rules implied by spinlocks.
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*
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* If IPIs can go out of order to the cache coherency protocol
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* in an architecture, sufficient synchronisation should be added
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* to arch code to make it appear to obey cache coherency WRT
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* locking and barrier primitives. Generic code isn't really
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* equipped to do the right thing...
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*/
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if (llist_add(node, &per_cpu(call_single_queue, cpu)))
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send_call_function_single_ipi(cpu);
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}
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/*
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* Insert a previously allocated call_single_data_t element
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* for execution on the given CPU. data must already have
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* ->func, ->info, and ->flags set.
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*/
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static int generic_exec_single(int cpu, call_single_data_t *csd,
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smp_call_func_t func, void *info)
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static int generic_exec_single(int cpu, call_single_data_t *csd)
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{
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if (cpu == smp_processor_id()) {
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smp_call_func_t func = csd->func;
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void *info = csd->info;
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unsigned long flags;
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/*
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@ -159,28 +175,12 @@ static int generic_exec_single(int cpu, call_single_data_t *csd,
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return 0;
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}
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if ((unsigned)cpu >= nr_cpu_ids || !cpu_online(cpu)) {
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csd_unlock(csd);
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return -ENXIO;
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}
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csd->func = func;
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csd->info = info;
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/*
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* The list addition should be visible before sending the IPI
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* handler locks the list to pull the entry off it because of
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* normal cache coherency rules implied by spinlocks.
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*
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* If IPIs can go out of order to the cache coherency protocol
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* in an architecture, sufficient synchronisation should be added
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* to arch code to make it appear to obey cache coherency WRT
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* locking and barrier primitives. Generic code isn't really
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* equipped to do the right thing...
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*/
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if (llist_add(&csd->llist, &per_cpu(call_single_queue, cpu)))
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send_call_function_single_ipi(cpu);
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__smp_call_single_queue(cpu, &csd->llist);
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return 0;
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}
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@ -194,16 +194,10 @@ static int generic_exec_single(int cpu, call_single_data_t *csd,
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void generic_smp_call_function_single_interrupt(void)
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{
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flush_smp_call_function_queue(true);
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/*
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* Handle irq works queued remotely by irq_work_queue_on().
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* Smp functions above are typically synchronous so they
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* better run first since some other CPUs may be busy waiting
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* for them.
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*/
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irq_work_run();
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}
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extern void irq_work_single(void *);
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/**
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* flush_smp_call_function_queue - Flush pending smp-call-function callbacks
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*
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* We don't have to use the _safe() variant here
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* because we are not invoking the IPI handlers yet.
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*/
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llist_for_each_entry(csd, entry, llist)
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pr_warn("IPI callback %pS sent to offline CPU\n",
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csd->func);
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llist_for_each_entry(csd, entry, llist) {
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switch (CSD_TYPE(csd)) {
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case CSD_TYPE_ASYNC:
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case CSD_TYPE_SYNC:
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case CSD_TYPE_IRQ_WORK:
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pr_warn("IPI callback %pS sent to offline CPU\n",
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csd->func);
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break;
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default:
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pr_warn("IPI callback, unknown type %d, sent to offline CPU\n",
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CSD_TYPE(csd));
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break;
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}
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}
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}
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/*
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*/
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prev = NULL;
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llist_for_each_entry_safe(csd, csd_next, entry, llist) {
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smp_call_func_t func = csd->func;
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void *info = csd->info;
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/* Do we wait until *after* callback? */
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if (csd->flags & CSD_FLAG_SYNCHRONOUS) {
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if (CSD_TYPE(csd) == CSD_TYPE_SYNC) {
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smp_call_func_t func = csd->func;
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void *info = csd->info;
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if (prev) {
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prev->next = &csd_next->llist;
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} else {
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entry = &csd_next->llist;
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}
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func(info);
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csd_unlock(csd);
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} else {
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* Second; run all !SYNC callbacks.
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*/
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llist_for_each_entry_safe(csd, csd_next, entry, llist) {
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smp_call_func_t func = csd->func;
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void *info = csd->info;
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int type = CSD_TYPE(csd);
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csd_unlock(csd);
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func(info);
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if (type == CSD_TYPE_ASYNC) {
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smp_call_func_t func = csd->func;
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void *info = csd->info;
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csd_unlock(csd);
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func(info);
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} else if (type == CSD_TYPE_IRQ_WORK) {
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irq_work_single(csd);
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}
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}
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}
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{
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call_single_data_t *csd;
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call_single_data_t csd_stack = {
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.flags = CSD_FLAG_LOCK | CSD_FLAG_SYNCHRONOUS,
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.flags = CSD_FLAG_LOCK | CSD_TYPE_SYNC,
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};
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int this_cpu;
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int err;
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csd_lock(csd);
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}
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err = generic_exec_single(cpu, csd, func, info);
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csd->func = func;
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csd->info = info;
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err = generic_exec_single(cpu, csd);
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if (wait)
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csd_lock_wait(csd);
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csd->flags = CSD_FLAG_LOCK;
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smp_wmb();
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err = generic_exec_single(cpu, csd, csd->func, csd->info);
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err = generic_exec_single(cpu, csd);
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out:
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preempt_enable();
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csd_lock(csd);
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if (wait)
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csd->flags |= CSD_FLAG_SYNCHRONOUS;
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csd->flags |= CSD_TYPE_SYNC;
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csd->func = func;
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csd->info = info;
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if (llist_add(&csd->llist, &per_cpu(call_single_queue, cpu)))
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{
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int num_nodes, num_cpus;
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/*
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* Ensure struct irq_work layout matches so that
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* flush_smp_call_function_queue() can do horrible things.
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*/
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BUILD_BUG_ON(offsetof(struct irq_work, llnode) !=
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offsetof(struct __call_single_data, llist));
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BUILD_BUG_ON(offsetof(struct irq_work, func) !=
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offsetof(struct __call_single_data, func));
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BUILD_BUG_ON(offsetof(struct irq_work, flags) !=
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offsetof(struct __call_single_data, flags));
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idle_threads_init();
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cpuhp_threads_init();
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