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drm/armada: provide pitches from armada_drm_plane_calc_addrs() 

Provide the framebuffer pitches from armada_drm_plane_calc_addrs() as
well as the base addresses for each plane.  Since this is now about
more than just addresses, rename to armada_drm_plane_calc().

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Russell King 2018-07-30 11:52:34 +01:00
parent b4df3ba0d7
commit 4aafe00e2f
3 changed files with 20 additions and 13 deletions
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8
drivers/gpu/drm/armada/armada_overlay.c
View File

@ -130,10 +130,10 @@ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane,
old_state->src.y1 != state->src.y1 || old_state->src.y1 != state->src.y1 ||
old_state->fb != state->fb) { old_state->fb != state->fb) {
const struct drm_format_info *format; const struct drm_format_info *format;
u16 src_x; u16 src_x, pitches[3];
u32 addrs[3]; u32 addrs[3];
armada_drm_plane_calc_addrs(state, addrs); armada_drm_plane_calc(state, addrs, pitches);
armada_reg_queue_set(regs, idx, addrs[0], armada_reg_queue_set(regs, idx, addrs[0],
LCD_SPU_DMA_START_ADDR_Y0); LCD_SPU_DMA_START_ADDR_Y0);
@ -148,9 +148,9 @@ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane,
armada_reg_queue_set(regs, idx, addrs[2], armada_reg_queue_set(regs, idx, addrs[2],
LCD_SPU_DMA_START_ADDR_V1); LCD_SPU_DMA_START_ADDR_V1);
val = state->fb->pitches[0] << 16 | state->fb->pitches[0]; val = pitches[0] << 16 | pitches[0];
armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC); armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC);
val = state->fb->pitches[1] << 16 | state->fb->pitches[2]; val = pitches[1] << 16 | pitches[2];
armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV); armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV);
cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) | cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) |

22
drivers/gpu/drm/armada/armada_plane.c
View File

@ -35,7 +35,8 @@ static const uint32_t armada_primary_formats[] = {
DRM_FORMAT_BGR565, DRM_FORMAT_BGR565,
}; };
void armada_drm_plane_calc_addrs(struct drm_plane_state *state, u32 addrs[3]) void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[3],
u16 pitches[3])
{ {
struct drm_framebuffer *fb = state->fb; struct drm_framebuffer *fb = state->fb;
const struct drm_format_info *format = fb->format; const struct drm_format_info *format = fb->format;
@ -53,37 +54,42 @@ void armada_drm_plane_calc_addrs(struct drm_plane_state *state, u32 addrs[3])
addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] + addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] +
x * format->cpp[0]; x * format->cpp[0];
pitches[0] = fb->pitches[0];
y /= format->vsub; y /= format->vsub;
x /= format->hsub; x /= format->hsub;
for (i = 1; i < num_planes; i++) for (i = 1; i < num_planes; i++) {
addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] + addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
x * format->cpp[i]; x * format->cpp[i];
for (; i < 3; i++) pitches[i] = fb->pitches[i];
}
for (; i < 3; i++) {
addrs[i] = 0; addrs[i] = 0;
pitches[i] = 0;
}
} }
static unsigned armada_drm_crtc_calc_fb(struct drm_plane_state *state, static unsigned armada_drm_crtc_calc_fb(struct drm_plane_state *state,
struct armada_regs *regs, bool interlaced) struct armada_regs *regs, bool interlaced)
{ {
unsigned pitch = state->fb->pitches[0]; u16 pitches[3];
u32 addrs[3], addr_odd, addr_even; u32 addrs[3], addr_odd, addr_even;
unsigned i = 0; unsigned i = 0;
armada_drm_plane_calc_addrs(state, addrs); armada_drm_plane_calc(state, addrs, pitches);
addr_odd = addr_even = addrs[0]; addr_odd = addr_even = addrs[0];
if (interlaced) { if (interlaced) {
addr_even += pitch; addr_even += pitches[0];
pitch *= 2; pitches[0] *= 2;
} }
/* write offset, base, and pitch */ /* write offset, base, and pitch */
armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0); armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1); armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH); armada_reg_queue_mod(regs, i, pitches[0], 0xffff, LCD_CFG_GRA_PITCH);
return i; return i;
} }

3
drivers/gpu/drm/armada/armada_plane.h
View File

@ -1,7 +1,8 @@
#ifndef ARMADA_PLANE_H #ifndef ARMADA_PLANE_H
#define ARMADA_PLANE_H #define ARMADA_PLANE_H
void armada_drm_plane_calc_addrs(struct drm_plane_state *state, u32 addrs[3]); void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[3],
u16 pitches[3]);
int armada_drm_plane_prepare_fb(struct drm_plane *plane, int armada_drm_plane_prepare_fb(struct drm_plane *plane,
struct drm_plane_state *state); struct drm_plane_state *state);
void armada_drm_plane_cleanup_fb(struct drm_plane *plane, void armada_drm_plane_cleanup_fb(struct drm_plane *plane,