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nios2: fix cache coherency issue when debug with gdb 

Remove the end address checking for flushda function. We need to flush
each address line for flushda instruction, from start to end address.
This is because flushda instruction only flush the cache if tag and line
fields are matched.

Change to use ldwio instruction (bypass cache) to load the instruction
that causing trap. Our interest is the actual instruction that executed
by the processor, this should be uncached.
Note, EA address might be an userspace cached address.


Signed-off-by: Ley Foon Tan <lftan@altera.com>
This commit is contained in:
Ley Foon Tan 2015-04-10 11:10:08 +08:00
parent e3e29f990c
commit 4a89c3088f
2 changed files with 1 additions and 4 deletions
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2
arch/nios2/kernel/entry.S
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@ -161,7 +161,7 @@ ENTRY(inthandler)
*********************************************************************** ***********************************************************************
*/ */
ENTRY(handle_trap) ENTRY(handle_trap)
ldw r24, -4(ea) /* instruction that caused the exception */ ldwio r24, -4(ea) /* instruction that caused the exception */
srli r24, r24, 4 srli r24, r24, 4
andi r24, r24, 0x7c andi r24, r24, 0x7c
movia r9,trap_table movia r9,trap_table

3
arch/nios2/mm/cacheflush.c
View File

@ -23,9 +23,6 @@ static void __flush_dcache(unsigned long start, unsigned long end)
end += (cpuinfo.dcache_line_size - 1); end += (cpuinfo.dcache_line_size - 1);
end &= ~(cpuinfo.dcache_line_size - 1); end &= ~(cpuinfo.dcache_line_size - 1);
if (end > start + cpuinfo.dcache_size)
end = start + cpuinfo.dcache_size;
for (addr = start; addr < end; addr += cpuinfo.dcache_line_size) { for (addr = start; addr < end; addr += cpuinfo.dcache_line_size) {
__asm__ __volatile__ (" flushda 0(%0)\n" __asm__ __volatile__ (" flushda 0(%0)\n"
: /* Outputs */ : /* Outputs */