drm/radeon/kms: add dpm support for rv6xx (v3)
This adds dpm support for rv6xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: remove duplicate line v3: fix thermal interrupt check noticed by Jerome Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
This commit is contained in:
Alex Deucher
parent
9d67006e6e
commit
4a6369e993
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@ -77,7 +77,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
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evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
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atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
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si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \
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r600_dpm.o rs780_dpm.o
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r600_dpm.o rs780_dpm.o rv6xx_dpm.o
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radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
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radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
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@ -3998,6 +3998,7 @@ int r600_irq_set(struct radeon_device *rdev)
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u32 hdmi0, hdmi1;
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u32 d1grph = 0, d2grph = 0;
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u32 dma_cntl;
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u32 thermal_int = 0;
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if (!rdev->irq.installed) {
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WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
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@ -4032,8 +4033,18 @@ int r600_irq_set(struct radeon_device *rdev)
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hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
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hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
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}
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dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
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if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
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thermal_int = RREG32(CG_THERMAL_INT) &
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~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
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if (rdev->irq.dpm_thermal) {
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DRM_DEBUG("dpm thermal\n");
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thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
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}
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}
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if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
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DRM_DEBUG("r600_irq_set: sw int\n");
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cp_int_cntl |= RB_INT_ENABLE;
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@ -4115,6 +4126,9 @@ int r600_irq_set(struct radeon_device *rdev)
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WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
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WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
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}
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if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
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WREG32(CG_THERMAL_INT, thermal_int);
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}
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return 0;
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}
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@ -4306,6 +4320,7 @@ int r600_irq_process(struct radeon_device *rdev)
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u32 ring_index;
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bool queue_hotplug = false;
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bool queue_hdmi = false;
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bool queue_thermal = false;
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if (!rdev->ih.enabled || rdev->shutdown)
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return IRQ_NONE;
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@ -4473,6 +4488,16 @@ restart_ih:
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DRM_DEBUG("IH: DMA trap\n");
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radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
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break;
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case 230: /* thermal low to high */
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DRM_DEBUG("IH: thermal low to high\n");
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rdev->pm.dpm.thermal.high_to_low = false;
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queue_thermal = true;
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break;
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case 231: /* thermal high to low */
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DRM_DEBUG("IH: thermal high to low\n");
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rdev->pm.dpm.thermal.high_to_low = true;
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queue_thermal = true;
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break;
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case 233: /* GUI IDLE */
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DRM_DEBUG("IH: GUI idle\n");
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break;
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@ -4489,6 +4514,8 @@ restart_ih:
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schedule_work(&rdev->hotplug_work);
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if (queue_hdmi)
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schedule_work(&rdev->audio_work);
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if (queue_thermal && rdev->pm.dpm_enabled)
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schedule_work(&rdev->pm.dpm.thermal.work);
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rdev->ih.rptr = rptr;
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WREG32(IH_RB_RPTR, rdev->ih.rptr);
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atomic_set(&rdev->ih.lock, 0);
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@ -676,3 +676,48 @@ bool r600_is_uvd_state(u32 class, u32 class2)
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return true;
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return false;
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}
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int r600_set_thermal_temperature_range(struct radeon_device *rdev,
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int min_temp, int max_temp)
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{
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int low_temp = 0 * 1000;
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int high_temp = 255 * 1000;
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if (low_temp < min_temp)
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low_temp = min_temp;
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if (high_temp > max_temp)
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high_temp = max_temp;
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if (high_temp < low_temp) {
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DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
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return -EINVAL;
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}
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WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
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WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
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WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
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rdev->pm.dpm.thermal.min_temp = low_temp;
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rdev->pm.dpm.thermal.max_temp = high_temp;
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return 0;
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}
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bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor)
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{
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switch (sensor) {
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case THERMAL_TYPE_RV6XX:
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case THERMAL_TYPE_RV770:
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case THERMAL_TYPE_EVERGREEN:
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case THERMAL_TYPE_SUMO:
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case THERMAL_TYPE_NI:
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return true;
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case THERMAL_TYPE_ADT7473_WITH_INTERNAL:
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case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
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return false; /* need special handling */
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case THERMAL_TYPE_NONE:
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case THERMAL_TYPE_EXTERNAL:
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case THERMAL_TYPE_EXTERNAL_GPIO:
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default:
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return false;
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}
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}
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@ -92,6 +92,10 @@
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#define R600_PM_NUMBER_OF_VOLTAGE_LEVELS 4
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#define R600_PM_NUMBER_OF_ACTIVITY_LEVELS 3
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/* XXX are these ok? */
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#define R600_TEMP_RANGE_MIN (90 * 1000)
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#define R600_TEMP_RANGE_MAX (120 * 1000)
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enum r600_power_level {
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R600_POWER_LEVEL_LOW = 0,
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R600_POWER_LEVEL_MEDIUM = 1,
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@ -207,4 +211,8 @@ void r600_wait_for_power_level(struct radeon_device *rdev,
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void r600_start_dpm(struct radeon_device *rdev);
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void r600_stop_dpm(struct radeon_device *rdev);
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int r600_set_thermal_temperature_range(struct radeon_device *rdev,
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int min_temp, int max_temp);
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bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor);
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#endif
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@ -302,10 +302,23 @@
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#define GRBM_SOFT_RESET 0x8020
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#define SOFT_RESET_CP (1<<0)
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#define CG_THERMAL_CTRL 0x7F0
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#define DIG_THERM_DPM(x) ((x) << 12)
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#define DIG_THERM_DPM_MASK 0x000FF000
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#define DIG_THERM_DPM_SHIFT 12
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#define CG_THERMAL_STATUS 0x7F4
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#define ASIC_T(x) ((x) << 0)
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#define ASIC_T_MASK 0x1FF
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#define ASIC_T_SHIFT 0
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#define CG_THERMAL_INT 0x7F8
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#define DIG_THERM_INTH(x) ((x) << 8)
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#define DIG_THERM_INTH_MASK 0x0000FF00
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#define DIG_THERM_INTH_SHIFT 8
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#define DIG_THERM_INTL(x) ((x) << 16)
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#define DIG_THERM_INTL_MASK 0x00FF0000
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#define DIG_THERM_INTL_SHIFT 16
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#define THERM_INT_MASK_HIGH (1 << 24)
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#define THERM_INT_MASK_LOW (1 << 25)
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#define HDP_HOST_PATH_CNTL 0x2C00
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#define HDP_NONSURFACE_BASE 0x2C04
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@ -227,6 +227,8 @@ void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
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u32 eng_clock, u32 mem_clock);
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int radeon_atom_get_voltage_step(struct radeon_device *rdev,
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u8 voltage_type, u16 *voltage_step);
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int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
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u16 voltage_id, u16 *voltage);
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int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
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u8 voltage_type,
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u16 nominal_voltage,
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@ -681,6 +683,7 @@ struct radeon_irq {
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bool hpd[RADEON_MAX_HPD_PINS];
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bool afmt[RADEON_MAX_AFMT_BLOCKS];
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union radeon_irq_stat_regs stat_regs;
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bool dpm_thermal;
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};
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int radeon_irq_kms_init(struct radeon_device *rdev);
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@ -1147,6 +1147,18 @@ static struct radeon_asic rv6xx_asic = {
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.set_clock_gating = NULL,
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.get_temperature = &rv6xx_get_temp,
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},
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.dpm = {
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.init = &rv6xx_dpm_init,
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.setup_asic = &rv6xx_setup_asic,
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.enable = &rv6xx_dpm_enable,
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.disable = &rv6xx_dpm_disable,
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.set_power_state = &rv6xx_dpm_set_power_state,
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.display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
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.fini = &rv6xx_dpm_fini,
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.get_sclk = &rv6xx_dpm_get_sclk,
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.get_mclk = &rv6xx_dpm_get_mclk,
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.print_power_state = &rv6xx_dpm_print_power_state,
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},
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.pflip = {
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.pre_page_flip = &rs600_pre_page_flip,
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.page_flip = &rs600_page_flip,
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@ -402,6 +402,18 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev);
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u32 r600_get_xclk(struct radeon_device *rdev);
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uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
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int rv6xx_get_temp(struct radeon_device *rdev);
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/* rv6xx dpm */
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int rv6xx_dpm_init(struct radeon_device *rdev);
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int rv6xx_dpm_enable(struct radeon_device *rdev);
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void rv6xx_dpm_disable(struct radeon_device *rdev);
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int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
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void rv6xx_setup_asic(struct radeon_device *rdev);
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void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
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void rv6xx_dpm_fini(struct radeon_device *rdev);
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u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
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u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
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void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
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struct radeon_ps *ps);
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/* rs780 dpm */
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int rs780_dpm_init(struct radeon_device *rdev);
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int rs780_dpm_enable(struct radeon_device *rdev);
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@ -2268,8 +2268,8 @@ static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r
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}
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}
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static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
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u16 *vddc, u16 *vddci)
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void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
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u16 *vddc, u16 *vddci)
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{
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struct radeon_mode_info *mode_info = &rdev->mode_info;
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int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
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@ -116,6 +116,7 @@ void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
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/* Disable *all* interrupts */
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for (i = 0; i < RADEON_NUM_RINGS; i++)
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atomic_set(&rdev->irq.ring_int[i], 0);
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rdev->irq.dpm_thermal = false;
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for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
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rdev->irq.hpd[i] = false;
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for (i = 0; i < RADEON_MAX_CRTCS; i++) {
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@ -163,6 +164,7 @@ void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
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/* Disable *all* interrupts */
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for (i = 0; i < RADEON_NUM_RINGS; i++)
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atomic_set(&rdev->irq.ring_int[i], 0);
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rdev->irq.dpm_thermal = false;
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for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
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rdev->irq.hpd[i] = false;
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for (i = 0; i < RADEON_MAX_CRTCS; i++) {
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@ -580,6 +580,8 @@ extern enum radeon_tv_std
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radeon_combios_get_tv_info(struct radeon_device *rdev);
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extern enum radeon_tv_std
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radeon_atombios_get_tv_info(struct radeon_device *rdev);
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extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
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u16 *vddc, u16 *vddci);
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extern struct drm_connector *
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radeon_get_connector_for_encoder(struct drm_encoder *encoder);
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@ -1030,6 +1030,11 @@ int radeon_pm_init(struct radeon_device *rdev)
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{
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/* enable dpm on rv6xx+ */
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switch (rdev->family) {
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case CHIP_RV610:
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case CHIP_RV630:
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case CHIP_RV620:
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case CHIP_RV635:
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case CHIP_RV670:
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case CHIP_RS780:
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case CHIP_RS880:
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if (radeon_dpm == 1)
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@ -1114,6 +1119,7 @@ static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
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if (rdev->pm.num_power_states < 2)
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return;
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INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
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mutex_lock(&rdev->pm.mutex);
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rdev->pm.active_crtcs = 0;
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@ -560,6 +560,12 @@ int rs780_dpm_enable(struct radeon_device *rdev)
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if (pi->gfx_clock_gating)
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r600_gfx_clockgating_enable(rdev, true);
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if (rdev->irq.installed && (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
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r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
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rdev->irq.dpm_thermal = true;
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radeon_irq_set(rdev);
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}
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return 0;
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}
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@ -574,6 +580,12 @@ void rs780_dpm_disable(struct radeon_device *rdev)
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if (pi->gfx_clock_gating)
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r600_gfx_clockgating_enable(rdev, false);
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if (rdev->irq.installed &&
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(rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
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rdev->irq.dpm_thermal = false;
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radeon_irq_set(rdev);
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}
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}
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int rs780_dpm_set_power_state(struct radeon_device *rdev)
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,95 @@
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/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#ifndef __RV6XX_DPM_H__
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#define __RV6XX_DPM_H__
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#include "r600_dpm.h"
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/* Represents a single SCLK step. */
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struct rv6xx_sclk_stepping
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{
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u32 vco_frequency;
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u32 post_divider;
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};
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struct rv6xx_pm_hw_state {
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u32 sclks[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
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u32 mclks[R600_PM_NUMBER_OF_MCLKS];
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u16 vddc[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
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bool backbias[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
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bool pcie_gen2[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
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u8 high_sclk_index;
|
||||
u8 medium_sclk_index;
|
||||
u8 low_sclk_index;
|
||||
u8 high_mclk_index;
|
||||
u8 medium_mclk_index;
|
||||
u8 low_mclk_index;
|
||||
u8 high_vddc_index;
|
||||
u8 medium_vddc_index;
|
||||
u8 low_vddc_index;
|
||||
u8 rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
|
||||
u8 lp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
|
||||
};
|
||||
|
||||
struct rv6xx_power_info {
|
||||
/* flags */
|
||||
bool voltage_control;
|
||||
bool sclk_ss;
|
||||
bool mclk_ss;
|
||||
bool dynamic_ss;
|
||||
bool dynamic_pcie_gen2;
|
||||
bool thermal_protection;
|
||||
bool display_gap;
|
||||
bool gfx_clock_gating;
|
||||
/* clk values */
|
||||
u32 fb_div_scale;
|
||||
u32 spll_ref_div;
|
||||
u32 mpll_ref_div;
|
||||
u32 bsu;
|
||||
u32 bsp;
|
||||
/* */
|
||||
u32 active_auto_throttle_sources;
|
||||
/* current power state */
|
||||
u32 restricted_levels;
|
||||
struct rv6xx_pm_hw_state hw;
|
||||
};
|
||||
|
||||
struct rv6xx_pl {
|
||||
u32 sclk;
|
||||
u32 mclk;
|
||||
u16 vddc;
|
||||
u32 flags;
|
||||
};
|
||||
|
||||
struct rv6xx_ps {
|
||||
struct rv6xx_pl high;
|
||||
struct rv6xx_pl medium;
|
||||
struct rv6xx_pl low;
|
||||
};
|
||||
|
||||
#define RV6XX_DEFAULT_VCLK_FREQ 40000 /* 10 khz */
|
||||
#define RV6XX_DEFAULT_DCLK_FREQ 30000 /* 10 khz */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,246 @@
|
|||
/*
|
||||
* Copyright 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef RV6XXD_H
|
||||
#define RV6XXD_H
|
||||
|
||||
/* RV6xx power management */
|
||||
#define SPLL_CNTL_MODE 0x60c
|
||||
# define SPLL_DIV_SYNC (1 << 5)
|
||||
|
||||
#define GENERAL_PWRMGT 0x618
|
||||
# define GLOBAL_PWRMGT_EN (1 << 0)
|
||||
# define STATIC_PM_EN (1 << 1)
|
||||
# define MOBILE_SU (1 << 2)
|
||||
# define THERMAL_PROTECTION_DIS (1 << 3)
|
||||
# define THERMAL_PROTECTION_TYPE (1 << 4)
|
||||
# define ENABLE_GEN2PCIE (1 << 5)
|
||||
# define SW_GPIO_INDEX(x) ((x) << 6)
|
||||
# define SW_GPIO_INDEX_MASK (3 << 6)
|
||||
# define LOW_VOLT_D2_ACPI (1 << 8)
|
||||
# define LOW_VOLT_D3_ACPI (1 << 9)
|
||||
# define VOLT_PWRMGT_EN (1 << 10)
|
||||
# define BACKBIAS_PAD_EN (1 << 16)
|
||||
# define BACKBIAS_VALUE (1 << 17)
|
||||
# define BACKBIAS_DPM_CNTL (1 << 18)
|
||||
# define DYN_SPREAD_SPECTRUM_EN (1 << 21)
|
||||
|
||||
#define MCLK_PWRMGT_CNTL 0x624
|
||||
# define MPLL_PWRMGT_OFF (1 << 0)
|
||||
# define YCLK_TURNOFF (1 << 1)
|
||||
# define MPLL_TURNOFF (1 << 2)
|
||||
# define SU_MCLK_USE_BCLK (1 << 3)
|
||||
# define DLL_READY (1 << 4)
|
||||
# define MC_BUSY (1 << 5)
|
||||
# define MC_INT_CNTL (1 << 7)
|
||||
# define MRDCKA_SLEEP (1 << 8)
|
||||
# define MRDCKB_SLEEP (1 << 9)
|
||||
# define MRDCKC_SLEEP (1 << 10)
|
||||
# define MRDCKD_SLEEP (1 << 11)
|
||||
# define MRDCKE_SLEEP (1 << 12)
|
||||
# define MRDCKF_SLEEP (1 << 13)
|
||||
# define MRDCKG_SLEEP (1 << 14)
|
||||
# define MRDCKH_SLEEP (1 << 15)
|
||||
# define MRDCKA_RESET (1 << 16)
|
||||
# define MRDCKB_RESET (1 << 17)
|
||||
# define MRDCKC_RESET (1 << 18)
|
||||
# define MRDCKD_RESET (1 << 19)
|
||||
# define MRDCKE_RESET (1 << 20)
|
||||
# define MRDCKF_RESET (1 << 21)
|
||||
# define MRDCKG_RESET (1 << 22)
|
||||
# define MRDCKH_RESET (1 << 23)
|
||||
# define DLL_READY_READ (1 << 24)
|
||||
# define USE_DISPLAY_GAP (1 << 25)
|
||||
# define USE_DISPLAY_URGENT_NORMAL (1 << 26)
|
||||
# define USE_DISPLAY_GAP_CTXSW (1 << 27)
|
||||
# define MPLL_TURNOFF_D2 (1 << 28)
|
||||
# define USE_DISPLAY_URGENT_CTXSW (1 << 29)
|
||||
|
||||
#define MPLL_FREQ_LEVEL_0 0x6e8
|
||||
# define LEVEL0_MPLL_POST_DIV(x) ((x) << 0)
|
||||
# define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0)
|
||||
# define LEVEL0_MPLL_FB_DIV(x) ((x) << 8)
|
||||
# define LEVEL0_MPLL_FB_DIV_MASK (0xfff << 8)
|
||||
# define LEVEL0_MPLL_REF_DIV(x) ((x) << 20)
|
||||
# define LEVEL0_MPLL_REF_DIV_MASK (0x3f << 20)
|
||||
# define LEVEL0_MPLL_DIV_EN (1 << 28)
|
||||
# define LEVEL0_DLL_BYPASS (1 << 29)
|
||||
# define LEVEL0_DLL_RESET (1 << 30)
|
||||
|
||||
#define VID_RT 0x6f8
|
||||
# define VID_CRT(x) ((x) << 0)
|
||||
# define VID_CRT_MASK (0x1fff << 0)
|
||||
# define VID_CRTU(x) ((x) << 13)
|
||||
# define VID_CRTU_MASK (7 << 13)
|
||||
# define SSTU(x) ((x) << 16)
|
||||
# define SSTU_MASK (7 << 16)
|
||||
# define VID_SWT(x) ((x) << 19)
|
||||
# define VID_SWT_MASK (0x1f << 19)
|
||||
# define BRT(x) ((x) << 24)
|
||||
# define BRT_MASK (0xff << 24)
|
||||
|
||||
#define TARGET_AND_CURRENT_PROFILE_INDEX 0x70c
|
||||
# define TARGET_PROFILE_INDEX_MASK (3 << 0)
|
||||
# define TARGET_PROFILE_INDEX_SHIFT 0
|
||||
# define CURRENT_PROFILE_INDEX_MASK (3 << 2)
|
||||
# define CURRENT_PROFILE_INDEX_SHIFT 2
|
||||
# define DYN_PWR_ENTER_INDEX(x) ((x) << 4)
|
||||
# define DYN_PWR_ENTER_INDEX_MASK (3 << 4)
|
||||
# define DYN_PWR_ENTER_INDEX_SHIFT 4
|
||||
# define CURR_MCLK_INDEX_MASK (3 << 6)
|
||||
# define CURR_MCLK_INDEX_SHIFT 6
|
||||
# define CURR_SCLK_INDEX_MASK (0x1f << 8)
|
||||
# define CURR_SCLK_INDEX_SHIFT 8
|
||||
# define CURR_VID_INDEX_MASK (3 << 13)
|
||||
# define CURR_VID_INDEX_SHIFT 13
|
||||
|
||||
#define VID_UPPER_GPIO_CNTL 0x740
|
||||
# define CTXSW_UPPER_GPIO_VALUES(x) ((x) << 0)
|
||||
# define CTXSW_UPPER_GPIO_VALUES_MASK (7 << 0)
|
||||
# define HIGH_UPPER_GPIO_VALUES(x) ((x) << 3)
|
||||
# define HIGH_UPPER_GPIO_VALUES_MASK (7 << 3)
|
||||
# define MEDIUM_UPPER_GPIO_VALUES(x) ((x) << 6)
|
||||
# define MEDIUM_UPPER_GPIO_VALUES_MASK (7 << 6)
|
||||
# define LOW_UPPER_GPIO_VALUES(x) ((x) << 9)
|
||||
# define LOW_UPPER_GPIO_VALUES_MASK (7 << 9)
|
||||
# define CTXSW_BACKBIAS_VALUE (1 << 12)
|
||||
# define HIGH_BACKBIAS_VALUE (1 << 13)
|
||||
# define MEDIUM_BACKBIAS_VALUE (1 << 14)
|
||||
# define LOW_BACKBIAS_VALUE (1 << 15)
|
||||
|
||||
#define CG_DISPLAY_GAP_CNTL 0x7dc
|
||||
# define DISP1_GAP(x) ((x) << 0)
|
||||
# define DISP1_GAP_MASK (3 << 0)
|
||||
# define DISP2_GAP(x) ((x) << 2)
|
||||
# define DISP2_GAP_MASK (3 << 2)
|
||||
# define VBI_TIMER_COUNT(x) ((x) << 4)
|
||||
# define VBI_TIMER_COUNT_MASK (0x3fff << 4)
|
||||
# define VBI_TIMER_UNIT(x) ((x) << 20)
|
||||
# define VBI_TIMER_UNIT_MASK (7 << 20)
|
||||
# define DISP1_GAP_MCHG(x) ((x) << 24)
|
||||
# define DISP1_GAP_MCHG_MASK (3 << 24)
|
||||
# define DISP2_GAP_MCHG(x) ((x) << 26)
|
||||
# define DISP2_GAP_MCHG_MASK (3 << 26)
|
||||
|
||||
#define CG_THERMAL_CTRL 0x7f0
|
||||
# define DPM_EVENT_SRC(x) ((x) << 0)
|
||||
# define DPM_EVENT_SRC_MASK (7 << 0)
|
||||
# define THERM_INC_CLK (1 << 3)
|
||||
# define TOFFSET(x) ((x) << 4)
|
||||
# define TOFFSET_MASK (0xff << 4)
|
||||
# define DIG_THERM_DPM(x) ((x) << 12)
|
||||
# define DIG_THERM_DPM_MASK (0xff << 12)
|
||||
# define CTF_SEL(x) ((x) << 20)
|
||||
# define CTF_SEL_MASK (7 << 20)
|
||||
# define CTF_PAD_POLARITY (1 << 23)
|
||||
# define CTF_PAD_EN (1 << 24)
|
||||
|
||||
#define CG_SPLL_SPREAD_SPECTRUM_LOW 0x820
|
||||
# define SSEN (1 << 0)
|
||||
# define CLKS(x) ((x) << 3)
|
||||
# define CLKS_MASK (0xff << 3)
|
||||
# define CLKS_SHIFT 3
|
||||
# define CLKV(x) ((x) << 11)
|
||||
# define CLKV_MASK (0x7ff << 11)
|
||||
# define CLKV_SHIFT 11
|
||||
#define CG_MPLL_SPREAD_SPECTRUM 0x830
|
||||
|
||||
#define CITF_CNTL 0x200c
|
||||
# define BLACKOUT_RD (1 << 0)
|
||||
# define BLACKOUT_WR (1 << 1)
|
||||
|
||||
#define RAMCFG 0x2408
|
||||
#define NOOFBANK_SHIFT 0
|
||||
#define NOOFBANK_MASK 0x00000001
|
||||
#define NOOFRANK_SHIFT 1
|
||||
#define NOOFRANK_MASK 0x00000002
|
||||
#define NOOFROWS_SHIFT 2
|
||||
#define NOOFROWS_MASK 0x0000001C
|
||||
#define NOOFCOLS_SHIFT 5
|
||||
#define NOOFCOLS_MASK 0x00000060
|
||||
#define CHANSIZE_SHIFT 7
|
||||
#define CHANSIZE_MASK 0x00000080
|
||||
#define BURSTLENGTH_SHIFT 8
|
||||
#define BURSTLENGTH_MASK 0x00000100
|
||||
#define CHANSIZE_OVERRIDE (1 << 10)
|
||||
|
||||
#define SQM_RATIO 0x2424
|
||||
# define STATE0(x) ((x) << 0)
|
||||
# define STATE0_MASK (0xff << 0)
|
||||
# define STATE1(x) ((x) << 8)
|
||||
# define STATE1_MASK (0xff << 8)
|
||||
# define STATE2(x) ((x) << 16)
|
||||
# define STATE2_MASK (0xff << 16)
|
||||
# define STATE3(x) ((x) << 24)
|
||||
# define STATE3_MASK (0xff << 24)
|
||||
|
||||
#define ARB_RFSH_CNTL 0x2460
|
||||
# define ENABLE (1 << 0)
|
||||
#define ARB_RFSH_RATE 0x2464
|
||||
# define POWERMODE0(x) ((x) << 0)
|
||||
# define POWERMODE0_MASK (0xff << 0)
|
||||
# define POWERMODE1(x) ((x) << 8)
|
||||
# define POWERMODE1_MASK (0xff << 8)
|
||||
# define POWERMODE2(x) ((x) << 16)
|
||||
# define POWERMODE2_MASK (0xff << 16)
|
||||
# define POWERMODE3(x) ((x) << 24)
|
||||
# define POWERMODE3_MASK (0xff << 24)
|
||||
|
||||
#define MC_SEQ_DRAM 0x2608
|
||||
# define CKE_DYN (1 << 12)
|
||||
|
||||
#define MC_SEQ_CMD 0x26c4
|
||||
|
||||
#define MC_SEQ_RESERVE_S 0x2890
|
||||
#define MC_SEQ_RESERVE_M 0x2894
|
||||
|
||||
#define LVTMA_DATA_SYNCHRONIZATION 0x7adc
|
||||
# define LVTMA_PFREQCHG (1 << 8)
|
||||
#define DCE3_LVTMA_DATA_SYNCHRONIZATION 0x7f98
|
||||
|
||||
/* PCIE indirect regs */
|
||||
#define PCIE_P_CNTL 0x40
|
||||
# define P_PLL_PWRDN_IN_L1L23 (1 << 3)
|
||||
# define P_PLL_BUF_PDNB (1 << 4)
|
||||
# define P_PLL_PDNB (1 << 9)
|
||||
# define P_ALLOW_PRX_FRONTEND_SHUTOFF (1 << 12)
|
||||
/* PCIE PORT indirect regs */
|
||||
#define PCIE_LC_CNTL 0xa0
|
||||
# define LC_L0S_INACTIVITY(x) ((x) << 8)
|
||||
# define LC_L0S_INACTIVITY_MASK (0xf << 8)
|
||||
# define LC_L0S_INACTIVITY_SHIFT 8
|
||||
# define LC_L1_INACTIVITY(x) ((x) << 12)
|
||||
# define LC_L1_INACTIVITY_MASK (0xf << 12)
|
||||
# define LC_L1_INACTIVITY_SHIFT 12
|
||||
# define LC_PMI_TO_L1_DIS (1 << 16)
|
||||
# define LC_ASPM_TO_L1_DIS (1 << 24)
|
||||
#define PCIE_LC_SPEED_CNTL 0xa4
|
||||
# define LC_GEN2_EN (1 << 0)
|
||||
# define LC_INITIATE_LINK_SPEED_CHANGE (1 << 7)
|
||||
# define LC_CURRENT_DATA_RATE (1 << 11)
|
||||
# define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12)
|
||||
# define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12)
|
||||
# define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12
|
||||
# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
|
||||
# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue